Pre-stitching tuning automation for panoramic vr applications

ABSTRACT

Methods, systems and apparatuses may provide for technology that identifies a seam area between a pair of images corresponding to a first eye and determines a disparity between the seam area and a reference area at a center line of a reference image corresponding to a second eye. The technology may also automatically adjust one or more pre-stitch parameters of camera sensors associated with the pair of images and the reference image based on the disparity.

TECHNICAL FIELD

Embodiments generally relate to graphics processing architectures. Moreparticularly, embodiments relate to pre-stitching tuning automation forpanoramic virtual reality (VR) applications.

BACKGROUND

Recent developments in immersive media technology enable a user wearinga virtual reality (VR) headset to view a live sporting event from aremote location as if the user were present at the event. The technologymay include placing a camera pod in the stands, wherein the camera podincludes multiple pairs of stereoscopic (e.g., left eye-right eye)cameras aimed in different directions. While images from the cameras maybe digitally “stitched” together to obtain a panoramic view of theevent, there remains considerable room for improvement. For example,each of the cameras may have slight calibration differences.Accordingly, parameters of the cameras may be manually adjusted prior tothe event to ensure that the images across the panoramic view areconsistent, wherein the manual adjustment procedure is time consuming,costly, and difficult to perform once the event has started.

BRIEF DESCRIPTION OF THE DRAWINGS

The various advantages of the embodiments will become apparent to oneskilled in the art by reading the following specification and appendedclaims, and by referencing the following drawings, in which:

FIG. 1 is a plan view of an example of a camera pod according to anembodiment;

FIG. 2 is a plan view of an example of the relative positioning of aplurality of camera sensors assigned to a particular eye according to anembodiment;

FIG. 3 is an illustration of an example of a seam area referencingscheme according to an embodiment;

FIG. 4 is a flowchart of an example of a method of operating aperformance-enhanced computing system according to an embodiment;

FIG. 5 is a flowchart of an example of a method of determiningdisparities between seam areas and reference areas according to anembodiment;

FIG. 6A is an illustration of an example of a transformation between aLagrange parent element and an irregular Lagrange element according toan embodiment;

FIG. 6B is an illustration of an example of the use of Lagrangetransformations to determine disparities according to an embodiment;

FIG. 7 is an illustration of an example a discretization of a Lagrangeparent element according to an embodiment;

FIG. 8 is a flowchart of an example of a method of maintaining one ormore pre-stitch parameters during a live event according to anembodiment;

FIG. 9 is a block diagram of an example of a performance-enhancedcomputing system according to an embodiment;

FIG. 10 is a block diagram of an example of a processing systemaccording to an embodiment;

FIG. 11 is a block diagram of an example of a processor according to anembodiment;

FIG. 12 is a block diagram of an example of a graphics processoraccording to an embodiment;

FIG. 13 is a block diagram of an example of a graphics processing engineof a graphics processor according to an embodiment;

FIG. 14 is a block diagram of an example of hardware logic of a graphicsprocessor core according to an embodiment;

FIGS. 15A to 15B illustrate an example of thread execution logicaccording to an embodiment;

FIG. 16 is a block diagram illustrating an example of a graphicsprocessor instruction formats according to an embodiment;

FIG. 17 is a block diagram of another example of a graphics processoraccording to an embodiment;

FIG. 18A is a block diagram illustrating an example of a graphicsprocessor command format according to an embodiment;

FIG. 18B is a block diagram illustrating an example of a graphicsprocessor command sequence according to an embodiment;

FIG. 19 illustrates an example graphics software architecture for a dataprocessing system according to an embodiment;

FIG. 20A is a block diagram illustrating an example of an IP coredevelopment system according to an embodiment;

FIG. 20B illustrates an example of a cross-section side view of anintegrated circuit package assembly according to an embodiment;

FIG. 21 is a block diagram illustrating an example of a system on a chipintegrated circuit according to an embodiment;

FIGS. 22A to 22B are block diagrams illustrating exemplary graphicsprocessors for use within an SoC, according to embodiments; and

FIGS. 23A to 23B illustrate additional exemplary graphics processorlogic according to embodiments.

DESCRIPTION OF EMBODIMENTS

Turning now to FIG. 1, a camera pod 30 is shown, wherein the camera pod30 is used to support an immersive media experience that enables a userwearing a VR headset (e.g., head-mounted display) to view a livesporting event from a remote location as if the user were present at theevent. In an embodiment, the camera pod 30 is placed at an advantageousviewing location in the stands (e.g., courtside seat location at abasketball game). The illustrated camera pod 30 includes a first pair 32(32 a, 32 b) of stereoscopic (e.g., left eye-right eye) camera sensors,a second pair 34 (34 a, 34 b) of stereoscopic camera sensors, a thirdpair 36 (36 a, 36 b) of stereoscopic camera sensors, a fourth pair 38(38 a, 38 b) of stereoscopic camera sensors, and a fifth pair 40 (40 a,40 b) of stereoscopic camera sensors. The first pair 32 includes a lefteye camera sensor 32 a and a right eye camera sensor 32 b, the secondpair 34 includes a left eye camera sensor 34 a and a right eye camerasensor 34 b, and so forth. Images from the camera pod 30 may bedigitally “stitched” together to obtain a panoramic view of the event.There may be, however, slight calibration differences across the camerasensors of the camera pod 30. Technology described herein enables thevisual impact of those differences to be minimized and/or eliminated.

With continuing reference to FIGS. 1 and 2, a seam (e.g., overlap) areamay be identified between, for example, images (e.g., panels) capturedby the left eye camera sensor 32 a and images captured by the left eyecamera sensor 34 a. As will be discussed in greater detail, imagescaptured by the right eye camera sensor 32 b generally include thecontent from the seam area between the images from the left eye camerasensor 32 a and the images from the left eye camera sensor 34 a. Indeed,a 36° separation between the right eye camera sensor 32 b and theadjacent left eye camera sensors 32 a, 34 a as shown, results in thecenter line of the images captured by the right eye camera sensor 32 baligning approximately with the middle of the seam area for the left eyecamera sensors 32 a, 34 a. Accordingly, a reference area (e.g., groundtruth) may be defined at the center line of the images captured by theright eye camera 32 b, wherein the reference area is used toautomatically ensure that the seam area is consistent and smooth from acolor (e.g., brightness, exposure), alignment and/or orientationstandpoint (e.g., accounting for sensor calibration differences). Usinga center line reference area from one eye (e.g., the right eye) tocorrect seam areas from the other eye (e.g., left eye) enables anautomated solution that is faster, less costly, and easier to performonce the event has started.

In one example, the same camera sensor is used to generate both the leftand right eye images for a given camera. Such a solution may be achievedby capturing the left eye image, rotating the camera sensor (e.g.,by)90°, and then capturing the right eye image. Thus, the first pair 32of stereoscopic camera sensors might be replaced with a single camerasensor that is rotated to capture both left eye images and right eyeimages, the second pair 34 of stereoscopic camera sensors may be placedwith a single camera sensor that is rotated to capture both left eyeimages and right eye images, and so forth.

In an embodiment, the camera sensor data is captured in a Bayer patternat 12-bit, 4096 by 2160 pixels, and 60 fps (frames per second) via GVSP(GigE Vision Stream Protocol). In a typical sports event broadcastingset up, the camera sensors are rotated vertically by 90° to give a widervertical field of view (VFOV) that is close to 90°. The horizontal fieldof view (HFOV) becomes 30° after the rotation of camera sensor. Thewider VFOV is advantageous for certain sports events such as basketballgames that require higher vertical view. The narrower HFOV iscompensated by the overlapping views of adjacent cameras. In oneexample, each stream of raw Bayer data is unpacked into RGB (red, green,blue) color format in a process called de-mosaicing.

FIG. 3 shows a seam area referencing scheme 42 in which thecorresponding reference areas (center lines, R_(n)) in the right eyeimage panels serve as a ground truth for the seams (stitching lines,L_(n)) in the left eye image panels. Thus, the center line R₁ is thereference for stitching line L₁, the center line R₂ is the reference forstitching line L₂, and so forth, in the illustrated example. Therectified RGB panels for each eye are mapped to a regular lattice viaperspective transformation to form a rectified arrangement 44 thatapproximates a cylindrical projection 46. The illustrated cylindricalprojection 46 forms a 180° panoramic image that may be converted intoYUV (luma and chrominance) color format. In one example, ahardware-accelerated technology matches blocks in the overlapping areasof one eye with blocks in the center line region of the other eye. Thetechnology may establish a correspondence between two regular parentalelement sets using, for example, minimum mean absolute difference (MAD)or mean squared error (MSE) criteria.

$\begin{matrix}{\min ( {\frac{1}{256^{2}}\Sigma_{i = 0}^{15}\Sigma_{j = 0}^{15}{{{L_{ij}( {x,y} )} - {R_{ij}( {{x + u},{y + v}} )}}}} )} & (1)\end{matrix}$

As already noted, the same camera sensor may be used to generate boththe left and right eye images for a given camera. Such a solution may beachieved by capturing the left eye image, rotating the camera sensor(e.g., by 90°), and then capturing the right eye image. Thus, a firstcamera sensor might generate the first image in a pair of (e.g., lefteye) images and the reference (e.g., right eye) image, wherein a secondcamera sensor generates the second image in the pair of images and thereference image corresponds to the first camera sensor being in arotated state.

FIG. 4 shows a method 50 of operating performance-enhanced computingsystem. The method 50 may be implemented as one or more modules in a setof logic instructions stored in a non-transitory machine- orcomputer-readable storage medium such as random access memory (RAM),read only memory (ROM), programmable ROM (PROM), firmware, flash memory,etc., in configurable logic such as, for example, programmable logicarrays (PLAs), field programmable gate arrays (FPGAs), complexprogrammable logic devices (CPLDs), in fixed-functionality hardwarelogic using circuit technology such as, for example, applicationspecific integrated circuit (ASIC), complementary metal oxidesemiconductor (CMOS) or transistor-transistor logic (TTL) technology, orany combination thereof.

For example, computer program code to carry out operations shown in themethod 50 may be written in any combination of one or more programminglanguages, including an object oriented programming language such asJAVA, SMALLTALK, C++ or the like and conventional procedural programminglanguages, such as the “C” programming language or similar programminglanguages. Additionally, logic instructions might include assemblerinstructions, instruction set architecture (ISA) instructions, machineinstructions, machine dependent instructions, microcode, state-settingdata, configuration data for integrated circuitry, state informationthat personalizes electronic circuitry and/or other structuralcomponents that are native to hardware (e.g., host processor, centralprocessing unit/CPU, microcontroller, etc.).

Illustrated processing block 52 identifies a seam area between a pair ofimages corresponding to a first eye. For example, block 52 mightidentify an area of overlap between the right edge of a first left eyeimage and the left edge of a second left eye image, wherein the firstand second left eye images are captured by camera sensors from adjacentpairs of stereoscopic cameras. Alternatively, block 52 may identify thearea of overlap between the left edge of a first right eye image and theright edge of a second right image, wherein the first and second righteye images are captured by camera sensors from adjacent pairs ofstereoscopic cameras.

Block 54 determines a disparity between the seam area and a referencearea at a center line of a reference image corresponding to a secondeye. For example, if the seam area is between the right edge of a firstleft eye image and the left edge of a second left eye image, thereference area might be taken from an image captured by the right eyecamera sensor of the stereoscopic camera that generates the first lefteye image. Alternatively, if the seam area is between the left edge of afirst right eye image and the right edge of a second right image, thereference area might be taken from an image captured by the left eyecamera sensor of the stereoscopic camera that generates the first righteye image.

As already noted, the reference image may be associated with a secondeye camera sensor positioned between a pair of first eye camera sensorsassociated with the pair of sensors. In an embodiment, block 54identifies a first set of nodal positions (e.g., anchors) in the seamarea based on a feature map and identifies a second set of nodalpositions in the reference area based on the first set of nodalpositions, wherein the disparity is determined between the first set ofnodal positions and the second set of nodal positions. As will bediscussed in greater detail, block 54 may also include compensating thedisparity for lens distortion and/or geometric distortion. Additionally,block 54 may include applying expression (1), discussed above.

Illustrated block 56 determines whether an acceptance threshold has beenreached. The acceptance threshold may be the minimum disparity accordingto expression (1) and/or another predefined and/or configurable value.If the acceptance threshold has not been reached, block 58 may adjustone or more pre-stitch parameters of camera sensors associated with thepair of images and the reference images based on the disparity. Thepre-stitch parameters may include, for example, color parameters (e.g.,brightness, exposure, gain), reference area width, alignment (e.g.,epipolar line position), orientation (e.g., epipolar line angle), etc.,or any combination thereof. Thus, block 58 might include, for example,automatically changing the reference area width and/or changing thebrightness of one or more of the pair of images (e.g., on a per nodalposition, pixel and/or pixel block basis). The illustrated method 50then returns to block 52. The illustrated method 50 is thereforeiterative in nature. If it is determined at block 56 that the acceptancethreshold has been reached, illustrated block 60 outputs the pre-stitchparameters to a stitch subsystem. The illustrated method 50 thereforeenhances performance via an automated solution that is faster, lesscostly, and easier to perform once the event has started.

FIG. 5 shows a method 62 of determining disparities between seam areasand reference areas. The method 62, which may be readily incorporatedinto block 54 (FIG. 4), already discussed, may generally be implementedin one or more modules as a set of logic instructions stored in amachine- or computer-readable storage medium such as RAM, ROM, PROM,firmware, flash memory, etc., in configurable logic such as, forexample, PLAs, FPGAs, CPLDs, in fixed-functionality hardware logic usingcircuit technology such as, for example, ASIC, CMOS, TTL technology, orany combination thereof.

Illustrated processing block 64 performs feature extraction in seam areaL_(n). In one example, block 64 uses a feature extraction filter such asa Gabor filter (e.g., a linear filter that analyzes whether there is anyspecific frequency content in the image in specific directions in alocalized region around the point or region of analysis) and outputs afeature map 66. Anchor points (e.g., nodal positions) are chosen atblock 68 using features with high energy content in the seam area L_(n).Illustrated block 68 generates an anchor map 70 that is used by block 72to perform block matching, which establishes a correspondence for anchorpoints in the reference area R_(n). Block 76 uses a correspondence map74 from block 72 to transform the images to Lagrange space, wherein thetransformation compensates for lens distortion and/or geometricdistortion in L_(n), and R_(n). Block 76 outputs Lagrange parentalelement pairs for L_(n), and R_(n), wherein a normalized MSE iscalculated at block 80 between transformed seams for one eye and thereference area for the other eye. The result of illustrated block 80 isa disparity measure 82 that may be used to automatically adjust one ormore pre-stitch parameters.

FIG. 6A demonstrates that the basic element of a Lagrange transformationis a nine-node element. More particularly, the transformation may bemade from an irregular Lagrange element 84 (D_(m)) to a Lagrange parentelement 86 (K_(m)). The deformed irregular Lagrange element 84, formedby nine anchor nodal points, becomes the rectangular element 86 aftercompensating for lens and/or geometric distortion in Lagrangetransformation. As will be discussed in greater detail, the Lagrangetransformation may be represented by a shape function.

FIG. 6B demonstrates the use of Lagrange transformations to determine adisparity 87. In the illustrated example, after correspondence betweenfeature points on left eye and right eye images has been established(e.g., L1˜>R1, L2˜>R2, . . . L9˜>R9), block matching (e.g., MAD, MSE,sum of absolute differences/SAD, etc.) is performed at node nine of theLagrange element.

FIG. 7 demonstrates that the intrinsic coordinates 88 in the parentelement 86 may be discretized into a discrete element 90. For example,if both the width and height of the element are sampled at 1/15, theelement represents a canvas in 41 by 41 pixels. Moreover, a shapefunction describes the deformation. The function within the Lagrangeelement can be interpolated from the nodal values of the element usingthe shape function. For example, the shape function of a nine-nodeLagrange element is given by,

N ₁=1/4(1−s ₁)(1−s ₂)−1/2N ₅−1/2N ₈+1/4N ₉

N ₂=1/4(1+s ₁)(1−s ₂)−1/2N ₅−1/2N ₆+1/4N ₉

N ₃=1/4(1+s ₁)(1+s ₂)−1/2N ₆−1/2N ₇+1/4N ₉

N ₄=1/4(1−s ₁)(1+s ₂)−1/2N ₇−1/2N ₈+1/4N ₉

N ₅=1/2(1−s ₁ ²)(1−s ₂)−1/2N ₉

N ₆=1/2(1+s ₁)(1−s2²)−1/2N ₉

N ₇=1/2(1−s ₁ ²)(1+s ₂)−1/2N ₉

N ₈=1/2(1−s ₁)(1−s ₂ ²)−1/2N ₉

N ₉=(1−s ₁ ²)(1−s ₂ ²)

In the above equations, variables s₁ and s₂ are the intrinsiccoordinates 88 in the parent element K_(m). The shape function has avalue of unity at the node to which it is related. The shape functionalso has the property that the sum at any point within an element isequal to unity.

FIG. 8 shows a method 92 of maintaining one or more stitch parametersduring a live event. The method 92 may generally be implemented in oneor more modules as a set of logic instructions stored in a machine- orcomputer-readable storage medium such as RAM, ROM, PROM, firmware, flashmemory, etc., in configurable logic such as, for example, PLAs, FPGAs,CPLDs, in fixed-functionality hardware logic using circuit technologysuch as, for example, ASIC, CMOS, TTL technology, or any combinationthereof.

Illustrated processing block 94 determines whether there is detectedmotion at the camera sensors capturing the live event. The motion may beindicative of, for example, someone bumping into the camera pod orotherwise changing the stability or position of the camera pod, whereinthe pre-stitch parameter(s) may no longer be effective or optimal. Block94 may include receiving and/or analyzing signals from gyroscopes,accelerometers and/or other inertial sensors mounted to the camerasensors and/or camera pod. In an embodiment, block 94 also includescomparing the detected motion to a predetermined and/or configurablethreshold. If motion is detected at block 94, illustrated block 96triggers a readjustment of the pre-stitch parameter(s). In one example,block 96 causes the method 50 (FIG. 4) to be repeated.

If it is determined at block 94 that the motion is not detected,illustrated block 98 determines whether an ambient lighting change isdetected at the camera sensors capturing the live event. The ambientlighting change may be indicative of, for example, sunset taking place,wherein the pre-stitch parameter(s) may no longer be effective oroptimal. Block 98 may include receiving and/or analyzing signals fromambient light sensors mounted to the camera sensors and/or camera pod.In an embodiment, block 98 also includes comparing the detected ambientlight change to a predetermined and/or configurable threshold. If anambient light change is detected at block 98, illustrated block 96triggers a readjustment of the pre-stitch parameter(s). In one example,block 96 causes the method 50 (FIG. 4) to be repeated. Thus, the method92 is particularly advantageous once the event being captured hasalready started.

FIG. 9 shows a computing system 150 that may generally be part of anelectronic device/system having computing functionality (e.g., personaldigital assistant/PDA, notebook computer, tablet computer, convertibletablet, server), communications functionality (e.g., smart phone),imaging functionality (e.g., camera, camcorder), media playingfunctionality (e.g., smart television/TV), wearable functionality (e.g.,watch, eyewear, headwear, footwear, jewelry), vehicular functionality(e.g., car, truck, motorcycle), robotic functionality (e.g., autonomousrobot), etc., or any combination thereof. In the illustrated example,the system 150 includes a graphics processor 152 (e.g., graphicsprocessing unit/GPU) and a host processor 154 (e.g., central processingunit/CPU) having one or more processor cores 156 and an integratedmemory controller (IMC) 158 that is coupled to a system memory 160.

Additionally, the illustrated system 150 includes an input output (IO)module 162 implemented together with the host processor 154, and thegraphics processor 152 on an SoC 164 (e.g., semiconductor die). In oneexample, the IO module 162 communicates with a display 166 (e.g., touchscreen, liquid crystal display/LCD, light emitting diode/LED display), anetwork controller 168 (e.g., wired and/or wireless), a plurality ofcameras 165, and mass storage 170 (e.g., hard disk drive/HDD, opticaldisk, solid state drive/SSD, flash memory). In an embodiment, thecameras 165 generate a pair of images corresponding to a first eye and areference image corresponding to a second eye.

The illustrated graphics processor 152 includes logic 174 (e.g., logicinstructions, configurable logic, fixed-functionality hardware logic,etc., or any combination thereof) to perform one or more aspects of themethod 50 (FIG. 4), the method 62 (FIG. 5) and/or the method 92 (FIG.8), already discussed. Thus, the logic 174 may automatically identify aseam area between a pair of images corresponding to a first eye andautomatically determine a disparity between the seam area and areference area at a center line of a reference image corresponding to asecond eye. The logic 174 may also adjust one or more pre-stitchparameters of the cameras 165, which are associated with the pair ofimages and the reference image, based on the disparity. In anembodiment, the reference image is associated with a second eye camerasensor positioned between a pair of first eye camera sensors associatedwith the pair of images. The illustrated system 150 may therefore beconsidered performance-enhanced to the extent that it is faster atadjusting pre-stitching parameters and less costly relative toconventional solutions. The system 150 also exhibits enhancedperformance because it automatically adjusts pre-stitching parametersonce the event has already started.

The SoC 164 may include one or more substrates (e.g., silicon, sapphire,gallium arsenide), wherein the logic 174 is a transistor array and otherintegrated circuit/IC components coupled to the substrate(s). In oneexample, the logic 174 includes transistor channel regions that arepositioned (e.g., embedded) within the substrate(s). Thus, the physicalinterface between the logic 174 and the substrate(s) may not be anabrupt junction. The logic 174 may also be considered to include anepitaxial layer that is grown on an initial wafer of the substrate(s).

System Overview

FIG. 10 is a block diagram of a processing system 100, according to anembodiment. In various embodiments the system 100 includes one or moreprocessors 102 and one or more graphics processors 108, and may be asingle processor desktop system, a multiprocessor workstation system, ora server system having a large number of processors 102 or processorcores 107. In one embodiment, the system 100 is a processing platformincorporated within a system-on-a-chip (SoC) integrated circuit for usein mobile, handheld, or embedded devices.

In one embodiment the system 100 can include, or be incorporated withina server-based gaming platform, a game console, including a game andmedia console, a mobile gaming console, a handheld game console, or anonline game console. In some embodiments the system 100 is a mobilephone, smart phone, tablet computing device or mobile Internet device.The processing system 100 can also include, couple with, or beintegrated within a wearable device, such as a smart watch wearabledevice, smart eyewear device, augmented reality device, or virtualreality device. In some embodiments, the processing system 100 is atelevision or set top box device having one or more processors 102 and agraphical interface generated by one or more graphics processors 108.

In some embodiments, the one or more processors 102 each include one ormore processor cores 107 to process instructions which, when executed,perform operations for system and user software. In some embodiments,each of the one or more processor cores 107 is configured to process aspecific instruction set 109. In some embodiments, instruction set 109may facilitate Complex Instruction Set Computing (CISC), ReducedInstruction Set Computing (RISC), or computing via a Very LongInstruction Word (VLIW). Multiple processor cores 107 may each process adifferent instruction set 109, which may include instructions tofacilitate the emulation of other instruction sets. Processor core 107may also include other processing devices, such a Digital SignalProcessor (DSP).

In some embodiments, the processor 102 includes cache memory 104.Depending on the architecture, the processor 102 can have a singleinternal cache or multiple levels of internal cache. In someembodiments, the cache memory is shared among various components of theprocessor 102. In some embodiments, the processor 102 also uses anexternal cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC))(not shown), which may be shared among processor cores 107 using knowncache coherency techniques. A register file 106 is additionally includedin processor 102 which may include different types of registers forstoring different types of data (e.g., integer registers, floating pointregisters, status registers, and an instruction pointer register). Someregisters may be general-purpose registers, while other registers may bespecific to the design of the processor 102.

In some embodiments, one or more processor(s) 102 are coupled with oneor more interface bus(es) 110 to transmit communication signals such asaddress, data, or control signals between processor 102 and othercomponents in the system 100. The interface bus 110, in one embodiment,can be a processor bus, such as a version of the Direct Media Interface(DMI) bus. However, processor busses are not limited to the DMI bus, andmay include one or more Peripheral Component Interconnect buses (e.g.,PCI, PCI Express), memory busses, or other types of interface busses. Inone embodiment the processor(s) 102 include an integrated memorycontroller 116 and a platform controller hub 130. The memory controller116 facilitates communication between a memory device and othercomponents of the system 100, while the platform controller hub (PCH)130 provides connections to I/O devices via a local I/O bus.

The memory device 120 can be a dynamic random access memory (DRAM)device, a static random access memory (SRAM) device, flash memorydevice, phase-change memory device, or some other memory device havingsuitable performance to serve as process memory. In one embodiment thememory device 120 can operate as system memory for the system 100, tostore data 122 and instructions 121 for use when the one or moreprocessors 102 executes an application or process. Memory controller 116also couples with an optional external graphics processor 112, which maycommunicate with the one or more graphics processors 108 in processors102 to perform graphics and media operations. In some embodiments adisplay device 111 can connect to the processor(s) 102. The displaydevice 111 can be one or more of an internal display device, as in amobile electronic device or a laptop device or an external displaydevice attached via a display interface (e.g., DisplayPort, etc.). Inone embodiment the display device 111 can be a head mounted display(HMD) such as a stereoscopic display device for use in virtual reality(VR) applications or augmented reality (AR) applications.

In some embodiments the platform controller hub 130 enables peripheralsto connect to memory device 120 and processor 102 via a high-speed I/Obus. The I/O peripherals include, but are not limited to, an audiocontroller 146, a network controller 134, a firmware interface 128, awireless transceiver 126, touch sensors 125, a data storage device 124(e.g., hard disk drive, flash memory, etc.). The data storage device 124can connect via a storage interface (e.g., SATA) or via a peripheralbus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCIExpress). The touch sensors 125 can include touch screen sensors,pressure sensors, or fingerprint sensors. The wireless transceiver 126can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile networktransceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver.The firmware interface 128 enables communication with system firmware,and can be, for example, a unified extensible firmware interface (UEFI).The network controller 134 can enable a network connection to a wirednetwork. In some embodiments, a high-performance network controller (notshown) couples with the interface bus 110. The audio controller 146, inone embodiment, is a multi-channel high definition audio controller. Inone embodiment the system 100 includes an optional legacy I/O controller140 for coupling legacy (e.g., Personal System 2 (PS/2)) devices to thesystem. The platform controller hub 130 can also connect to one or moreUniversal Serial Bus (USB) controllers 142 connect input devices, suchas keyboard and mouse 143 combinations, a camera 144, or other USB inputdevices.

It will be appreciated that the system 100 shown is exemplary and notlimiting, as other types of data processing systems that are differentlyconfigured may also be used. For example, an instance of the memorycontroller 116 and platform controller hub 130 may be integrated into adiscreet external graphics processor, such as the external graphicsprocessor 112. In one embodiment the platform controller hub 130 and/ormemory controller 116 may be external to the one or more processor(s)102. For example, the system 100 can include an external memorycontroller 116 and platform controller hub 130, which may be configuredas a memory controller hub and peripheral controller hub within a systemchipset that is in communication with the processor(s) 102.

FIG. 11 is a block diagram of an embodiment of a processor 200 havingone or more processor cores 202A-202N, an integrated memory controller214, and an integrated graphics processor 208. Those elements of FIG. 11having the same reference numbers (or names) as the elements of anyother figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such. Processor200 can include additional cores up to and including additional core202N represented by the dashed lined boxes. Each of processor cores202A-202N includes one or more internal cache units 204A-204N. In someembodiments each processor core also has access to one or more sharedcached units 206.

The internal cache units 204A-204N and shared cache units 206 representa cache memory hierarchy within the processor 200. The cache memoryhierarchy may include at least one level of instruction and data cachewithin each processor core and one or more levels of shared mid-levelcache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or otherlevels of cache, where the highest level of cache before external memoryis classified as the LLC. In some embodiments, cache coherency logicmaintains coherency between the various cache units 206 and 204A-204N.

In some embodiments, processor 200 may also include a set of one or morebus controller units 216 and a system agent core 210. The one or morebus controller units 216 manage a set of peripheral buses, such as oneor more PCI or PCI express busses. System agent core 210 providesmanagement functionality for the various processor components. In someembodiments, system agent core 210 includes one or more integratedmemory controllers 214 to manage access to various external memorydevices (not shown).

In some embodiments, one or more of the processor cores 202A-202Ninclude support for simultaneous multi-threading. In such embodiment,the system agent core 210 includes components for coordinating andoperating cores 202A-202N during multi-threaded processing. System agentcore 210 may additionally include a power control unit (PCU), whichincludes logic and components to regulate the power state of processorcores 202A-202N and graphics processor 208.

In some embodiments, processor 200 additionally includes graphicsprocessor 208 to execute graphics processing operations. In someembodiments, the graphics processor 208 couples with the set of sharedcache units 206, and the system agent core 210, including the one ormore integrated memory controllers 214. In some embodiments, the systemagent core 210 also includes a display controller 211 to drive graphicsprocessor output to one or more coupled displays. In some embodiments,display controller 211 may also be a separate module coupled with thegraphics processor via at least one interconnect, or may be integratedwithin the graphics processor 208.

In some embodiments, a ring based interconnect unit 212 is used tocouple the internal components of the processor 200. However, analternative interconnect unit may be used, such as a point-to-pointinterconnect, a switched interconnect, or other techniques, includingtechniques well known in the art. In some embodiments, graphicsprocessor 208 couples with the ring interconnect unit 212 via an I/Olink 213.

The exemplary I/O link 213 represents at least one of multiple varietiesof I/O interconnects, including an on package I/O interconnect whichfacilitates communication between various processor components and ahigh-performance embedded memory module 218, such as an eDRAM module. Insome embodiments, each of the processor cores 202A-202N and graphicsprocessor 208 use embedded memory modules 218 as a shared Last LevelCache.

In some embodiments, processor cores 202A-202N are homogenous coresexecuting the same instruction set architecture. In another embodiment,processor cores 202A-202N are heterogeneous in terms of instruction setarchitecture (ISA), where one or more of processor cores 202A-202Nexecute a first instruction set, while at least one of the other coresexecutes a subset of the first instruction set or a differentinstruction set. In one embodiment processor cores 202A-202N areheterogeneous in terms of microarchitecture, where one or more coreshaving a relatively higher power consumption couple with one or morepower cores having a lower power consumption. Additionally, processor200 can be implemented on one or more chips or as an SoC integratedcircuit having the illustrated components, in addition to othercomponents.

FIG. 12 is a block diagram of a graphics processor 300, which may be adiscrete graphics processing unit, or may be a graphics processorintegrated with a plurality of processing cores. In some embodiments,the graphics processor communicates via a memory mapped I/O interface toregisters on the graphics processor and with commands placed into theprocessor memory. In some embodiments, graphics processor 300 includes amemory interface 314 to access memory. Memory interface 314 can be aninterface to local memory, one or more internal caches, one or moreshared external caches, and/or to system memory.

In some embodiments, graphics processor 300 also includes a displaycontroller 302 to drive display output data to a display device 320.Display controller 302 includes hardware for one or more overlay planesfor the display and composition of multiple layers of video or userinterface elements. The display device 320 can be an internal orexternal display device. In one embodiment the display device 320 is ahead mounted display device, such as a virtual reality (VR) displaydevice or an augmented reality (AR) display device. In some embodiments,graphics processor 300 includes a video codec engine 306 to encode,decode, or transcode media to, from, or between one or more mediaencoding formats, including, but not limited to Moving Picture ExpertsGroup (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formatssuch as H.264/MPEG-4 AVC, as well as the Society of Motion Picture &Television Engineers (SMPTE) 421M/VC-1, and Joint Photographic ExpertsGroup (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats.

In some embodiments, graphics processor 300 includes a block imagetransfer (BLIT) engine 304 to perform two-dimensional (2D) rasterizeroperations including, for example, bit-boundary block transfers.However, in one embodiment, 2D graphics operations are performed usingone or more components of graphics processing engine (GPE) 310. In someembodiments, GPE 310 is a compute engine for performing graphicsoperations, including three-dimensional (3D) graphics operations andmedia operations.

In some embodiments, GPE 310 includes a 3D pipeline 312 for performing3D operations, such as rendering three-dimensional images and scenesusing processing functions that act upon 3D primitive shapes (e.g.,rectangle, triangle, etc.). The 3D pipeline 312 includes programmableand fixed function elements that perform various tasks within theelement and/or spawn execution threads to a 3D/Media sub-system 315.While 3D pipeline 312 can be used to perform media operations, anembodiment of GPE 310 also includes a media pipeline 316 that isspecifically used to perform media operations, such as videopost-processing and image enhancement.

In some embodiments, media pipeline 316 includes fixed function orprogrammable logic units to perform one or more specialized mediaoperations, such as video decode acceleration, video de-interlacing, andvideo encode acceleration in place of, or on behalf of video codecengine 306. In some embodiments, media pipeline 316 additionallyincludes a thread spawning unit to spawn threads for execution on3D/Media sub-system 315. The spawned threads perform computations forthe media operations on one or more graphics execution units included in3D/Media sub-system 315.

In some embodiments, 3D/Media subsystem 315 includes logic for executingthreads spawned by 3D pipeline 312 and media pipeline 316. In oneembodiment, the pipelines send thread execution requests to 3D/Mediasubsystem 315, which includes thread dispatch logic for arbitrating anddispatching the various requests to available thread executionresources. The execution resources include an array of graphicsexecution units to process the 3D and media threads. In someembodiments, 3D/Media subsystem 315 includes one or more internal cachesfor thread instructions and data. In some embodiments, the subsystemalso includes shared memory, including registers and addressable memory,to share data between threads and to store output data.

Graphics Processing Engine

FIG. 13 is a block diagram of a graphics processing engine 410 of agraphics processor in accordance with some embodiments. In oneembodiment, the graphics processing engine (GPE) 410 is a version of theGPE 310 shown in FIG. 12. Elements of FIG. 13 having the same referencenumbers (or names) as the elements of any other figure herein canoperate or function in any manner similar to that described elsewhereherein, but are not limited to such. For example, the 3D pipeline 312and media pipeline 316 of FIG. 12 are illustrated. The media pipeline316 is optional in some embodiments of the GPE 410 and may not beexplicitly included within the GPE 410. For example and in at least oneembodiment, a separate media and/or image processor is coupled to theGPE 410.

In some embodiments, GPE 410 couples with or includes a command streamer403, which provides a command stream to the 3D pipeline 312 and/or mediapipelines 316. In some embodiments, command streamer 403 is coupled withmemory, which can be system memory, or one or more of internal cachememory and shared cache memory. In some embodiments, command streamer403 receives commands from the memory and sends the commands to 3Dpipeline 312 and/or media pipeline 316. The commands are directivesfetched from a ring buffer, which stores commands for the 3D pipeline312 and media pipeline 316. In one embodiment, the ring buffer canadditionally include batch command buffers storing batches of multiplecommands. The commands for the 3D pipeline 312 can also includereferences to data stored in memory, such as but not limited to vertexand geometry data for the 3D pipeline 312 and/or image data and memoryobjects for the media pipeline 316. The 3D pipeline 312 and mediapipeline 316 process the commands and data by performing operations vialogic within the respective pipelines or by dispatching one or moreexecution threads to a graphics core array 414. In one embodiment thegraphics core array 414 include one or more blocks of graphics cores(e.g., graphics core(s) 415A, graphics core(s) 415B), each blockincluding one or more graphics cores. Each graphics core includes a setof graphics execution resources that includes general-purpose andgraphics specific execution logic to perform graphics and computeoperations, as well as fixed function texture processing and/or machinelearning and artificial intelligence acceleration logic.

In various embodiments the 3D pipeline 312 includes fixed function andprogrammable logic to process one or more shader programs, such asvertex shaders, geometry shaders, pixel shaders, fragment shaders,compute shaders, or other shader programs, by processing theinstructions and dispatching execution threads to the graphics corearray 414. The graphics core array 414 provides a unified block ofexecution resources for use in processing these shader programs.Multi-purpose execution logic (e.g., execution units) within thegraphics core(s) 415A-414B of the graphic core array 414 includessupport for various 3D API shader languages and can execute multiplesimultaneous execution threads associated with multiple shaders.

In some embodiments the graphics core array 414 also includes executionlogic to perform media functions, such as video and/or image processing.In one embodiment, the execution units additionally includegeneral-purpose logic that is programmable to perform parallelgeneral-purpose computational operations, in addition to graphicsprocessing operations. The general-purpose logic can perform processingoperations in parallel or in conjunction with general-purpose logicwithin the processor core(s) 107 of FIG. 10 or core 202A-202N as in FIG.11.

Output data generated by threads executing on the graphics core array414 can output data to memory in a unified return buffer (URB) 418. TheURB 418 can store data for multiple threads. In some embodiments the URB418 may be used to send data between different threads executing on thegraphics core array 414. In some embodiments the URB 418 mayadditionally be used for synchronization between threads on the graphicscore array and fixed function logic within the shared function logic420.

In some embodiments, graphics core array 414 is scalable, such that thearray includes a variable number of graphics cores, each having avariable number of execution units based on the target power andperformance level of GPE 410. In one embodiment the execution resourcesare dynamically scalable, such that execution resources may be enabledor disabled as needed.

The graphics core array 414 couples with shared function logic 420 thatincludes multiple resources that are shared between the graphics coresin the graphics core array. The shared functions within the sharedfunction logic 420 are hardware logic units that provide specializedsupplemental functionality to the graphics core array 414. In variousembodiments, shared function logic 420 includes but is not limited tosampler 421, math 422, and inter-thread communication (ITC) 423 logic.Additionally, some embodiments implement one or more cache(s) 425 withinthe shared function logic 420.

A shared function is implemented where the demand for a givenspecialized function is insufficient for inclusion within the graphicscore array 414. Instead a single instantiation of that specializedfunction is implemented as a stand-alone entity in the shared functionlogic 420 and shared among the execution resources within the graphicscore array 414. The precise set of functions that are shared between thegraphics core array 414 and included within the graphics core array 414varies across embodiments. In some embodiments, specific sharedfunctions within the shared function logic 420 that are used extensivelyby the graphics core array 414 may be included within shared functionlogic 416 within the graphics core array 414. In various embodiments,the shared function logic 416 within the graphics core array 414 caninclude some or all logic within the shared function logic 420. In oneembodiment, all logic elements within the shared function logic 420 maybe duplicated within the shared function logic 416 of the graphics corearray 414. In one embodiment the shared function logic 420 is excludedin favor of the shared function logic 416 within the graphics core array414.

FIG. 14 is a block diagram of hardware logic of a graphics processorcore 500, according to some embodiments described herein. Elements ofFIG. 14 having the same reference numbers (or names) as the elements ofany other figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such. Theillustrated graphics processor core 500, in some embodiments, isincluded within the graphics core array 414 of FIG. 13. The graphicsprocessor core 500, sometimes referred to as a core slice, can be one ormultiple graphics cores within a modular graphics processor. Thegraphics processor core 500 is exemplary of one graphics core slice, anda graphics processor as described herein may include multiple graphicscore slices based on target power and performance envelopes. Eachgraphics processor core 500 can include a fixed function block 530coupled with multiple sub-cores 501A-501F, also referred to assub-slices, that include modular blocks of general-purpose and fixedfunction logic.

In some embodiments the fixed function block 530 includes ageometry/fixed function pipeline 536 that can be shared by all sub-coresin the graphics processor core 500, for example, in lower performanceand/or lower power graphics processor implementations. In variousembodiments, the geometry/fixed function pipeline 536 includes a 3Dfixed function pipeline (e.g., 3D pipeline 312 as in FIG. 12 and FIG.13) a video front-end unit, a thread spawner and thread dispatcher, anda unified return buffer manager, which manages unified return buffers,such as the unified return buffer 418 of FIG. 13.

In one embodiment the fixed function block 530 also includes a graphicsSoC interface 537, a graphics microcontroller 538, and a media pipeline539. The graphics SoC interface 537 provides an interface between thegraphics processor core 500 and other processor cores within a system ona chip integrated circuit. The graphics microcontroller 538 is aprogrammable sub-processor that is configurable to manage variousfunctions of the graphics processor core 500, including thread dispatch,scheduling, and pre-emption. The media pipeline 539 (e.g., mediapipeline 316 of FIG. 12 and FIG. 13) includes logic to facilitate thedecoding, encoding, pre-processing, and/or post-processing of multimediadata, including image and video data. The media pipeline 539 implementmedia operations via requests to compute or sampling logic within thesub-cores 501-501F.

In one embodiment the SoC interface 537 enables the graphics processorcore 500 to communicate with general-purpose application processor cores(e.g., CPUs) and/or other components within an SoC, including memoryhierarchy elements such as a shared last level cache memory, the systemRAM, and/or embedded on-chip or on-package DRAM. The SoC interface 537can also enable communication with fixed function devices within theSoC, such as camera imaging pipelines, and enables the use of and/orimplements global memory atomics that may be shared between the graphicsprocessor core 500 and CPUs within the SoC. The SoC interface 537 canalso implement power management controls for the graphics processor core500 and enable an interface between a clock domain of the graphic core500 and other clock domains within the SoC. In one embodiment the SoCinterface 537 enables receipt of command buffers from a command streamerand global thread dispatcher that are configured to provide commands andinstructions to each of one or more graphics cores within a graphicsprocessor. The commands and instructions can be dispatched to the mediapipeline 539, when media operations are to be performed, or a geometryand fixed function pipeline (e.g., geometry and fixed function pipeline536, geometry and fixed function pipeline 514) when graphics processingoperations are to be performed.

The graphics microcontroller 538 can be configured to perform variousscheduling and management tasks for the graphics processor core 500. Inone embodiment the graphics microcontroller 538 can perform graphicsand/or compute workload scheduling on the various graphics parallelengines within execution unit (EU) arrays 502A-502F, 504A-504F withinthe sub-cores 501A-501F. In this scheduling model, host softwareexecuting on a CPU core of an SoC including the graphics processor core500 can submit workloads one of multiple graphic processor doorbells,which invokes a scheduling operation on the appropriate graphics engine.Scheduling operations include determining which workload to run next,submitting a workload to a command streamer, pre-empting existingworkloads running on an engine, monitoring progress of a workload, andnotifying host software when a workload is complete. In one embodimentthe graphics microcontroller 538 can also facilitate low-power or idlestates for the graphics processor core 500, providing the graphicsprocessor core 500 with the ability to save and restore registers withinthe graphics processor core 500 across low-power state transitionsindependently from the operating system and/or graphics driver softwareon the system.

The graphics processor core 500 may have greater than or fewer than theillustrated sub-cores 501A-501F, up to N modular sub-cores. For each setof N sub-cores, the graphics processor core 500 can also include sharedfunction logic 510, shared and/or cache memory 512, a geometry/fixedfunction pipeline 514, as well as additional fixed function logic 516 toaccelerate various graphics and compute processing operations. Theshared function logic 510 can include logic units associated with theshared function logic 420 of FIG. 13 (e.g., sampler, math, and/orinter-thread communication logic) that can be shared by each N sub-coreswithin the graphics processor core 500. The shared and/or cache memory512 can be a last-level cache for the set of N sub-cores 501A-501Fwithin the graphics processor core 500, and can also serve as sharedmemory that is accessible by multiple sub-cores. The geometry/fixedfunction pipeline 514 can be included instead of the geometry/fixedfunction pipeline 536 within the fixed function block 530 and caninclude the same or similar logic units.

In one embodiment the graphics processor core 500 includes additionalfixed function logic 516 that can include various fixed functionacceleration logic for use by the graphics processor core 500. In oneembodiment the additional fixed function logic 516 includes anadditional geometry pipeline for use in position only shading. Inposition-only shading, two geometry pipelines exist, the full geometrypipeline within the geometry/fixed function pipeline 516, 536, and acull pipeline, which is an additional geometry pipeline which may beincluded within the additional fixed function logic 516. In oneembodiment the cull pipeline is a trimmed down version of the fullgeometry pipeline. The full pipeline and the cull pipeline can executedifferent instances of the same application, each instance having aseparate context. Position only shading can hide long cull runs ofdiscarded triangles, enabling shading to be completed earlier in someinstances. For example and in one embodiment the cull pipeline logicwithin the additional fixed function logic 516 can execute positionshaders in parallel with the main application and generally generatescritical results faster than the full pipeline, as the cull pipelinefetches and shades only the position attribute of the vertices, withoutperforming rasterization and rendering of the pixels to the framebuffer. The cull pipeline can use the generated critical results tocompute visibility information for all the triangles without regard towhether those triangles are culled. The full pipeline (which in thisinstance may be referred to as a replay pipeline) can consume thevisibility information to skip the culled triangles to shade only thevisible triangles that are finally passed to the rasterization phase.

In one embodiment the additional fixed function logic 516 can alsoinclude machine-learning acceleration logic, such as fixed functionmatrix multiplication logic, for implementations including optimizationsfor machine learning training or inferencing.

Within each graphics sub-core 501A-501F includes a set of executionresources that may be used to perform graphics, media, and computeoperations in response to requests by graphics pipeline, media pipeline,or shader programs. The graphics sub-cores 501A-501F include multiple EUarrays 502A-502F, 504A-504F, thread dispatch and inter-threadcommunication (TD/IC) logic 503A-503F, a 3D (e.g., texture) sampler505A-505F, a media sampler 506A-506F, a shader processor 507A-507F, andshared local memory (SLM) 508A-508F. The EU arrays 502A-502F, 504A-504Feach include multiple execution units, which are general-purposegraphics processing units capable of performing floating-point andinteger/fixed-point logic operations in service of a graphics, media, orcompute operation, including graphics, media, or compute shaderprograms. The TD/IC logic 503A-503F performs local thread dispatch andthread control operations for the execution units within a sub-core andfacilitate communication between threads executing on the executionunits of the sub-core. The 3D sampler 505A-505F can read texture orother 3D graphics related data into memory. The 3D sampler can readtexture data differently based on a configured sample state and thetexture format associated with a given texture. The media sampler506A-506F can perform similar read operations based on the type andformat associated with media data. In one embodiment, each graphicssub-core 501A-501F can alternately include a unified 3D and mediasampler. Threads executing on the execution units within each of thesub-cores 501A-501F can make use of shared local memory 508A-508F withineach sub-core, to enable threads executing within a thread group toexecute using a common pool of on-chip memory.

Execution Units

FIGS. 15A-15B illustrate thread execution logic 600 including an arrayof processing elements employed in a graphics processor core accordingto embodiments described herein. Elements of FIGS. 15A-15B having thesame reference numbers (or names) as the elements of any other figureherein can operate or function in any manner similar to that describedelsewhere herein, but are not limited to such. FIG. 15A illustrates anoverview of thread execution logic 600, which can include a variant ofthe hardware logic illustrated with each sub-core 501A-501F of FIG. 14.FIG. 15B illustrates exemplary internal details of an execution unit.

As illustrated in FIG. 15A, in some embodiments thread execution logic600 includes a shader processor 602, a thread dispatcher 604,instruction cache 606, a scalable execution unit array including aplurality of execution units 608A-608N, a sampler 610, a data cache 612,and a data port 614. In one embodiment the scalable execution unit arraycan dynamically scale by enabling or disabling one or more executionunits (e.g., any of execution unit 608A, 608B, 608C, 608D, through608N-1 and 608N) based on the computational requirements of a workload.In one embodiment the included components are interconnected via aninterconnect fabric that links to each of the components. In someembodiments, thread execution logic 600 includes one or more connectionsto memory, such as system memory or cache memory, through one or more ofinstruction cache 606, data port 614, sampler 610, and execution units608A-608N. In some embodiments, each execution unit (e.g. 608A) is astand-alone programmable general-purpose computational unit that iscapable of executing multiple simultaneous hardware threads whileprocessing multiple data elements in parallel for each thread. Invarious embodiments, the array of execution units 608A-608N is scalableto include any number individual execution units.

In some embodiments, the execution units 608A-608N are primarily used toexecute shader programs. A shader processor 602 can process the variousshader programs and dispatch execution threads associated with theshader programs via a thread dispatcher 604. In one embodiment thethread dispatcher includes logic to arbitrate thread initiation requestsfrom the graphics and media pipelines and instantiate the requestedthreads on one or more execution unit in the execution units 608A-608N.For example, a geometry pipeline can dispatch vertex, tessellation, orgeometry shaders to the thread execution logic for processing. In someembodiments, thread dispatcher 604 can also process runtime threadspawning requests from the executing shader programs.

In some embodiments, the execution units 608A-608N support aninstruction set that includes native support for many standard 3Dgraphics shader instructions, such that shader programs from graphicslibraries (e.g., Direct 3D and OpenGL) are executed with a minimaltranslation. The execution units support vertex and geometry processing(e.g., vertex programs, geometry programs, vertex shaders), pixelprocessing (e.g., pixel shaders, fragment shaders) and general-purposeprocessing (e.g., compute and media shaders). Each of the executionunits 608A-608N is capable of multi-issue single instruction multipledata (SIMD) execution and multi-threaded operation enables an efficientexecution environment in the face of higher latency memory accesses.Each hardware thread within each execution unit has a dedicatedhigh-bandwidth register file and associated independent thread-state.Execution is multi-issue per clock to pipelines capable of integer,single and double precision floating point operations, SIMD branchcapability, logical operations, transcendental operations, and othermiscellaneous operations. While waiting for data from memory or one ofthe shared functions, dependency logic within the execution units608A-608N causes a waiting thread to sleep until the requested data hasbeen returned. While the waiting thread is sleeping, hardware resourcesmay be devoted to processing other threads. For example, during a delayassociated with a vertex shader operation, an execution unit can performoperations for a pixel shader, fragment shader, or another type ofshader program, including a different vertex shader.

Each execution unit in execution units 608A-608N operates on arrays ofdata elements. The number of data elements is the “execution size,” orthe number of channels for the instruction. An execution channel is alogical unit of execution for data element access, masking, and flowcontrol within instructions. The number of channels may be independentof the number of physical Arithmetic Logic Units (ALUs) or FloatingPoint Units (FPUs) for a particular graphics processor. In someembodiments, execution units 608A-608N support integer andfloating-point data types.

The execution unit instruction set includes SIMD instructions. Thevarious data elements can be stored as a packed data type in a registerand the execution unit will process the various elements based on thedata size of the elements. For example, when operating on a 256-bit widevector, the 256 bits of the vector are stored in a register and theexecution unit operates on the vector as four separate 64-bit packeddata elements (Quad-Word (QW) size data elements), eight separate 32-bitpacked data elements (Double Word (DW) size data elements), sixteenseparate 16-bit packed data elements (Word (W) size data elements), orthirty-two separate 8-bit data elements (byte (B) size data elements).However, different vector widths and register sizes are possible.

In one embodiment one or more execution units can be combined into afused execution unit 609A-609N having thread control logic (607A-607N)that is common to the fused EUs. Multiple EUs can be fused into an EUgroup. Each EU in the fused EU group can be configured to execute aseparate SIMD hardware thread. The number of EUs in a fused EU group canvary according to embodiments. Additionally, various SIMD widths can beperformed per-EU, including but not limited to SIMD8, SIMD16, andSIMD32. Each fused graphics execution unit 609A-609N includes at leasttwo execution units. For example, fused execution unit 609A includes afirst EU 608A, second EU 608B, and thread control logic 607A that iscommon to the first EU 608A and the second EU 608B. The thread controllogic 607A controls threads executed on the fused graphics executionunit 609A, allowing each EU within the fused execution units 609A-609Nto execute using a common instruction pointer register.

One or more internal instruction caches (e.g., 606) are included in thethread execution logic 600 to cache thread instructions for theexecution units. In some embodiments, one or more data caches (e.g.,612) are included to cache thread data during thread execution. In someembodiments, a sampler 610 is included to provide texture sampling for3D operations and media sampling for media operations. In someembodiments, sampler 610 includes specialized texture or media samplingfunctionality to process texture or media data during the samplingprocess before providing the sampled data to an execution unit.

During execution, the graphics and media pipelines send threadinitiation requests to thread execution logic 600 via thread spawningand dispatch logic. Once a group of geometric objects has been processedand rasterized into pixel data, pixel processor logic (e.g., pixelshader logic, fragment shader logic, etc.) within the shader processor602 is invoked to further compute output information and cause resultsto be written to output surfaces (e.g., color buffers, depth buffers,stencil buffers, etc.). In some embodiments, a pixel shader or fragmentshader calculates the values of the various vertex attributes that areto be interpolated across the rasterized object. In some embodiments,pixel processor logic within the shader processor 602 then executes anapplication programming interface (API)-supplied pixel or fragmentshader program. To execute the shader program, the shader processor 602dispatches threads to an execution unit (e.g., 608A) via threaddispatcher 604. In some embodiments, shader processor 602 uses texturesampling logic in the sampler 610 to access texture data in texture mapsstored in memory. Arithmetic operations on the texture data and theinput geometry data compute pixel color data for each geometricfragment, or discards one or more pixels from further processing.

In some embodiments, the data port 614 provides a memory accessmechanism for the thread execution logic 600 to output processed data tomemory for further processing on a graphics processor output pipeline.In some embodiments, the data port 614 includes or couples to one ormore cache memories (e.g., data cache 612) to cache data for memoryaccess via the data port.

As illustrated in FIG. 15B, a graphics execution unit 608 can include aninstruction fetch unit 637, a general register file array (GRF) 624, anarchitectural register file array (ARF) 626, a thread arbiter 622, asend unit 630, a branch unit 632, a set of SIMD floating point units(FPUs) 634, and in one embodiment a set of dedicated integer SIMD ALUs635. The GRF 624 and ARF 626 includes the set of general register filesand architecture register files associated with each simultaneoushardware thread that may be active in the graphics execution unit 608.In one embodiment, per thread architectural state is maintained in theARF 626, while data used during thread execution is stored in the GRF624. The execution state of each thread, including the instructionpointers for each thread, can be held in thread-specific registers inthe ARF 626.

In one embodiment the graphics execution unit 608 has an architecturethat is a combination of Simultaneous Multi-Threading (SMT) andfine-grained Interleaved Multi-Threading (IMT). The architecture has amodular configuration that can be fine tuned at design time based on atarget number of simultaneous threads and number of registers perexecution unit, where execution unit resources are divided across logicused to execute multiple simultaneous threads.

In one embodiment, the graphics execution unit 608 can co-issue multipleinstructions, which may each be different instructions. The threadarbiter 622 of the graphics execution unit thread 608 can dispatch theinstructions to one of the send unit 630, branch unit 632, or SIMDFPU(s) 634 for execution. Each execution thread can access 128general-purpose registers within the GRF 624, where each register canstore 32 bytes, accessible as a SIMD 8-element vector of 32-bit dataelements. In one embodiment, each execution unit thread has access to 4Kbytes within the GRF 624, although embodiments are not so limited, andgreater or fewer register resources may be provided in otherembodiments. In one embodiment up to seven threads can executesimultaneously, although the number of threads per execution unit canalso vary according to embodiments. In an embodiment in which seventhreads may access 4 Kbytes, the GRF 624 can store a total of 28 Kbytes.Flexible addressing modes can permit registers to be addressed togetherto build effectively wider registers or to represent strided rectangularblock data structures.

In one embodiment, memory operations, sampler operations, and otherlonger-latency system communications are dispatched via “send”instructions that are executed by the message passing send unit 630. Inone embodiment, branch instructions are dispatched to a dedicated branchunit 632 to facilitate SIMD divergence and eventual convergence.

In one embodiment the graphics execution unit 608 includes one or moreSIMD floating point units (FPU(s)) 634 to perform floating-pointoperations. In one embodiment, the FPU(s) 634 also support integercomputation. In one embodiment the FPU(s) 634 can SIMD execute up to Mnumber of 32-bit floating-point (or integer) operations, or SIMD executeup to 2M 16-bit integer or 16-bit floating-point operations. In oneembodiment, at least one of the FPU(s) provides extended math capabilityto support high-throughput transcendental math functions and doubleprecision 64-bit floating-point. In some embodiments, a set of 8-bitinteger SIMD ALUs 635 are also present, and may be specificallyoptimized to perform operations associated with machine learningcomputations.

In one embodiment, arrays of multiple instances of the graphicsexecution unit 608 can be instantiated in a graphics sub-core grouping(e.g., a sub-slice). For scalability, product architects can chose theexact number of execution units per sub-core grouping. In one embodimentthe execution unit 608 can execute instructions across a plurality ofexecution channels. In a further embodiment, each thread executed on thegraphics execution unit 608 is executed on a different channel.

FIG. 16 is a block diagram illustrating a graphics processor instructionformats 700 according to some embodiments. In one or more embodiment,the graphics processor execution units support an instruction set havinginstructions in multiple formats. The solid lined boxes illustrate thecomponents that are generally included in an execution unit instruction,while the dashed lines include components that are optional or that areonly included in a sub-set of the instructions. In some embodiments,instruction format 700 described and illustrated are macro-instructions,in that they are instructions supplied to the execution unit, as opposedto micro-operations resulting from instruction decode once theinstruction is processed.

In some embodiments, the graphics processor execution units nativelysupport instructions in a 128-bit instruction format 710. A 64-bitcompacted instruction format 730 is available for some instructionsbased on the selected instruction, instruction options, and number ofoperands. The native 128-bit instruction format 710 provides access toall instruction options, while some options and operations arerestricted in the 64-bit format 730. The native instructions availablein the 64-bit format 730 vary by embodiment. In some embodiments, theinstruction is compacted in part using a set of index values in an indexfield 713. The execution unit hardware references a set of compactiontables based on the index values and uses the compaction table outputsto reconstruct a native instruction in the 128-bit instruction format710.

For each format, instruction opcode 712 defines the operation that theexecution unit is to perform. The execution units execute eachinstruction in parallel across the multiple data elements of eachoperand. For example, in response to an add instruction the executionunit performs a simultaneous add operation across each color channelrepresenting a texture element or picture element. By default, theexecution unit performs each instruction across all data channels of theoperands. In some embodiments, instruction control field 714 enablescontrol over certain execution options, such as channels selection(e.g., predication) and data channel order (e.g., swizzle). Forinstructions in the 128-bit instruction format 710 an exec-size field716 limits the number of data channels that will be executed inparallel. In some embodiments, exec-size field 716 is not available foruse in the 64-bit compact instruction format 730.

Some execution unit instructions have up to three operands including twosource operands, src0 720, src1 722, and one destination 718. In someembodiments, the execution units support dual destination instructions,where one of the destinations is implied. Data manipulation instructionscan have a third source operand (e.g., SRC2 724), where the instructionopcode 712 determines the number of source operands. An instruction'slast source operand can be an immediate (e.g., hard-coded) value passedwith the instruction.

In some embodiments, the 128-bit instruction format 710 includes anaccess/address mode field 726 specifying, for example, whether directregister addressing mode or indirect register addressing mode is used.When direct register addressing mode is used, the register address ofone or more operands is directly provided by bits in the instruction.

In some embodiments, the 128-bit instruction format 710 includes anaccess/address mode field 726, which specifies an address mode and/or anaccess mode for the instruction. In one embodiment the access mode isused to define a data access alignment for the instruction. Someembodiments support access modes including a 16-byte aligned access modeand a 1-byte aligned access mode, where the byte alignment of the accessmode determines the access alignment of the instruction operands. Forexample, when in a first mode, the instruction may use byte-alignedaddressing for source and destination operands and when in a secondmode, the instruction may use 16-byte-aligned addressing for all sourceand destination operands.

In one embodiment, the address mode portion of the access/address modefield 726 determines whether the instruction is to use direct orindirect addressing. When direct register addressing mode is used bitsin the instruction directly provide the register address of one or moreoperands. When indirect register addressing mode is used, the registeraddress of one or more operands may be computed based on an addressregister value and an address immediate field in the instruction.

In some embodiments instructions are grouped based on opcode 712bit-fields to simplify Opcode decode 740. For an 8-bit opcode, bits 4,5, and 6 allow the execution unit to determine the type of opcode. Theprecise opcode grouping shown is merely an example. In some embodiments,a move and logic opcode group 742 includes data movement and logicinstructions (e.g., move (mov), compare (cmp)). In some embodiments,move and logic group 742 shares the five most significant bits (MSB),where move (mov) instructions are in the form of 0000xxxxb and logicinstructions are in the form of 0001xxxxb. A flow control instructiongroup 744 (e.g., call, jump (jmp)) includes instructions in the form of0010xxxxb (e.g., 0x20). A miscellaneous instruction group 746 includes amix of instructions, including synchronization instructions (e.g., wait,send) in the form of 0011xxxxb (e.g., 0x30). A parallel math instructiongroup 748 includes component-wise arithmetic instructions (e.g., add,multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel mathgroup 748 performs the arithmetic operations in parallel across datachannels. The vector math group 750 includes arithmetic instructions(e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math groupperforms arithmetic such as dot product calculations on vector operands.

Graphics Pipeline

FIG. 17 is a block diagram of another embodiment of a graphics processor800. Elements of FIG. 17 having the same reference numbers (or names) asthe elements of any other figure herein can operate or function in anymanner similar to that described elsewhere herein, but are not limitedto such.

In some embodiments, graphics processor 800 includes a geometry pipeline820, a media pipeline 830, a display engine 840, thread execution logic850, and a render output pipeline 870. In some embodiments, graphicsprocessor 800 is a graphics processor within a multi-core processingsystem that includes one or more general-purpose processing cores. Thegraphics processor is controlled by register writes to one or morecontrol registers (not shown) or via commands issued to graphicsprocessor 800 via a ring interconnect 802. In some embodiments, ringinterconnect 802 couples graphics processor 800 to other processingcomponents, such as other graphics processors or general-purposeprocessors. Commands from ring interconnect 802 are interpreted by acommand streamer 803, which supplies instructions to individualcomponents of the geometry pipeline 820 or the media pipeline 830.

In some embodiments, command streamer 803 directs the operation of avertex fetcher 805 that reads vertex data from memory and executesvertex-processing commands provided by command streamer 803. In someembodiments, vertex fetcher 805 provides vertex data to a vertex shader807, which performs coordinate space transformation and lightingoperations to each vertex. In some embodiments, vertex fetcher 805 andvertex shader 807 execute vertex-processing instructions by dispatchingexecution threads to execution units 852A-852B via a thread dispatcher831.

In some embodiments, execution units 852A-852B are an array of vectorprocessors having an instruction set for performing graphics and mediaoperations. In some embodiments, execution units 852A-852B have anattached L1 cache 851 that is specific for each array or shared betweenthe arrays. The cache can be configured as a data cache, an instructioncache, or a single cache that is partitioned to contain data andinstructions in different partitions.

In some embodiments, geometry pipeline 820 includes tessellationcomponents to perform hardware-accelerated tessellation of 3D objects.In some embodiments, a programmable hull shader 811 configures thetessellation operations. A programmable domain shader 817 providesback-end evaluation of tessellation output. A tessellator 813 operatesat the direction of hull shader 811 and contains special purpose logicto generate a set of detailed geometric objects based on a coarsegeometric model that is provided as input to geometry pipeline 820. Insome embodiments, if tessellation is not used, tessellation components(e.g., hull shader 811, tessellator 813, and domain shader 817) can bebypassed.

In some embodiments, complete geometric objects can be processed by ageometry shader 819 via one or more threads dispatched to executionunits 852A-852B, or can proceed directly to the clipper 829. In someembodiments, the geometry shader operates on entire geometric objects,rather than vertices or patches of vertices as in previous stages of thegraphics pipeline. If the tessellation is disabled the geometry shader819 receives input from the vertex shader 807. In some embodiments,geometry shader 819 is programmable by a geometry shader program toperform geometry tessellation if the tessellation units are disabled. Asdiscussed in detail above, if conditions permit the geometry shader maybe omitted or bypassed and primitive replication and various geometryshader logic may be moved to the vertex shader.

Before rasterization, a clipper 829 processes vertex data. The clipper829 may be a fixed function clipper or a programmable clipper havingclipping and geometry shader functions. In some embodiments, arasterizer and depth test component 873 in the render output pipeline870 dispatches pixel shaders to convert the geometric objects into perpixel representations. In some embodiments, pixel shader logic isincluded in thread execution logic 850. In some embodiments, anapplication can bypass the rasterizer and depth test component 873 andaccess un-rasterized vertex data via a stream out unit 823.

The graphics processor 800 has an interconnect bus, interconnect fabric,or some other interconnect mechanism that allows data and messagepassing amongst the major components of the processor. In someembodiments, execution units 852A-852B and associated logic units (e.g.,L1 cache 851, sampler 854, texture cache 858, etc.) interconnect via adata port 856 to perform memory access and communicate with renderoutput pipeline components of the processor. In some embodiments,sampler 854, caches 851, 858 and execution units 852A-852B each haveseparate memory access paths. In one embodiment the texture cache 858can also be configured as a sampler cache.

In some embodiments, render output pipeline 870 contains a rasterizerand depth test component 873 that converts vertex-based objects into anassociated pixel-based representation. In some embodiments, therasterizer logic includes a windower/masker unit to perform fixedfunction triangle and line rasterization. An associated render cache 878and depth cache 879 are also available in some embodiments. A pixeloperations component 877 performs pixel-based operations on the data,though in some instances, pixel operations associated with 2D operations(e.g. bit block image transfers with blending) are performed by the 2Dengine 841, or substituted at display time by the display controller 843using overlay display planes. In some embodiments, a shared L3 cache 875is available to all graphics components, allowing the sharing of datawithout the use of main system memory.

In some embodiments, graphics processor media pipeline 830 includes amedia engine 837 and a video front-end 834. In some embodiments, videofront-end 834 receives pipeline commands from the command streamer 803.In some embodiments, media pipeline 830 includes a separate commandstreamer. In some embodiments, video front-end 834 processes mediacommands before sending the command to the media engine 837. In someembodiments, media engine 837 includes thread spawning functionality tospawn threads for dispatch to thread execution logic 850 via threaddispatcher 831.

In some embodiments, graphics processor 800 includes a display engine840. In some embodiments, display engine 840 is external to processor800 and couples with the graphics processor via the ring interconnect802, or some other interconnect bus or fabric. In some embodiments,display engine 840 includes a 2D engine 841 and a display controller843. In some embodiments, display engine 840 contains special purposelogic capable of operating independently of the 3D pipeline. In someembodiments, display controller 843 couples with a display device (notshown), which may be a system integrated display device, as in a laptopcomputer, or an external display device attached via a display deviceconnector.

In some embodiments, the geometry pipeline 820 and media pipeline 830are configurable to perform operations based on multiple graphics andmedia programming interfaces and are not specific to any one applicationprogramming interface (API). In some embodiments, driver software forthe graphics processor translates API calls that are specific to aparticular graphics or media library into commands that can be processedby the graphics processor. In some embodiments, support is provided forthe Open Graphics Library (OpenGL), Open Computing Language (OpenCL),and/or Vulkan graphics and compute API, all from the Khronos Group. Insome embodiments, support may also be provided for the Direct3D libraryfrom the Microsoft Corporation. In some embodiments, a combination ofthese libraries may be supported. Support may also be provided for theOpen Source Computer Vision Library (OpenCV). A future API with acompatible 3D pipeline would also be supported if a mapping can be madefrom the pipeline of the future API to the pipeline of the graphicsprocessor.

Graphics Pipeline Programming

FIG. 18A is a block diagram illustrating a graphics processor commandformat 900 according to some embodiments. FIG. 18B is a block diagramillustrating a graphics processor command sequence 910 according to anembodiment. The solid lined boxes in FIG. 18A illustrate the componentsthat are generally included in a graphics command while the dashed linesinclude components that are optional or that are only included in asub-set of the graphics commands. The exemplary graphics processorcommand format 900 of FIG. 18A includes data fields to identify a client902, a command operation code (opcode) 904, and data 906 for thecommand. A sub-opcode 905 and a command size 908 are also included insome commands.

In some embodiments, client 902 specifies the client unit of thegraphics device that processes the command data. In some embodiments, agraphics processor command parser examines the client field of eachcommand to condition the further processing of the command and route thecommand data to the appropriate client unit. In some embodiments, thegraphics processor client units include a memory interface unit, arender unit, a 2D unit, a 3D unit, and a media unit. Each client unithas a corresponding processing pipeline that processes the commands.Once the command is received by the client unit, the client unit readsthe opcode 904 and, if present, sub-opcode 905 to determine theoperation to perform. The client unit performs the command usinginformation in data field 906. For some commands an explicit commandsize 908 is expected to specify the size of the command. In someembodiments, the command parser automatically determines the size of atleast some of the commands based on the command opcode. In someembodiments commands are aligned via multiples of a double word.

The flow diagram in FIG. 18B illustrates an exemplary graphics processorcommand sequence 910. In some embodiments, software or firmware of adata processing system that features an embodiment of a graphicsprocessor uses a version of the command sequence shown to set up,execute, and terminate a set of graphics operations. A sample commandsequence is shown and described for purposes of example only asembodiments are not limited to these specific commands or to thiscommand sequence. Moreover, the commands may be issued as batch ofcommands in a command sequence, such that the graphics processor willprocess the sequence of commands in at least partially concurrence.

In some embodiments, the graphics processor command sequence 910 maybegin with a pipeline flush command 912 to cause any active graphicspipeline to complete the currently pending commands for the pipeline. Insome embodiments, the 3D pipeline 922 and the media pipeline 924 do notoperate concurrently. The pipeline flush is performed to cause theactive graphics pipeline to complete any pending commands. In responseto a pipeline flush, the command parser for the graphics processor willpause command processing until the active drawing engines completepending operations and the relevant read caches are invalidated.Optionally, any data in the render cache that is marked ‘dirty’ can beflushed to memory. In some embodiments, pipeline flush command 912 canbe used for pipeline synchronization or before placing the graphicsprocessor into a low power state.

In some embodiments, a pipeline select command 913 is used when acommand sequence requires the graphics processor to explicitly switchbetween pipelines. In some embodiments, a pipeline select command 913 isrequired only once within an execution context before issuing pipelinecommands unless the context is to issue commands for both pipelines. Insome embodiments, a pipeline flush command 912 is required immediatelybefore a pipeline switch via the pipeline select command 913.

In some embodiments, a pipeline control command 914 configures agraphics pipeline for operation and is used to program the 3D pipeline922 and the media pipeline 924. In some embodiments, pipeline controlcommand 914 configures the pipeline state for the active pipeline. Inone embodiment, the pipeline control command 914 is used for pipelinesynchronization and to clear data from one or more cache memories withinthe active pipeline before processing a batch of commands.

In some embodiments, return buffer state commands 916 are used toconfigure a set of return buffers for the respective pipelines to writedata. Some pipeline operations require the allocation, selection, orconfiguration of one or more return buffers into which the operationswrite intermediate data during processing. In some embodiments, thegraphics processor also uses one or more return buffers to store outputdata and to perform cross thread communication. In some embodiments, thereturn buffer state 916 includes selecting the size and number of returnbuffers to use for a set of pipeline operations.

The remaining commands in the command sequence differ based on theactive pipeline for operations. Based on a pipeline determination 920,the command sequence is tailored to the 3D pipeline 922 beginning withthe 3D pipeline state 930 or the media pipeline 924 beginning at themedia pipeline state 940.

The commands to configure the 3D pipeline state 930 include 3D statesetting commands for vertex buffer state, vertex element state, constantcolor state, depth buffer state, and other state variables that are tobe configured before 3D primitive commands are processed. The values ofthese commands are determined at least in part based on the particular3D API in use. In some embodiments, 3D pipeline state 930 commands arealso able to selectively disable or bypass certain pipeline elements ifthose elements will not be used.

In some embodiments, 3D primitive 932 command is used to submit 3Dprimitives to be processed by the 3D pipeline. Commands and associatedparameters that are passed to the graphics processor via the 3Dprimitive 932 command are forwarded to the vertex fetch function in thegraphics pipeline. The vertex fetch function uses the 3D primitive 932command data to generate vertex data structures. The vertex datastructures are stored in one or more return buffers. In someembodiments, 3D primitive 932 command is used to perform vertexoperations on 3D primitives via vertex shaders. To process vertexshaders, 3D pipeline 922 dispatches shader execution threads to graphicsprocessor execution units.

In some embodiments, 3D pipeline 922 is triggered via an execute 934command or event. In some embodiments, a register write triggers commandexecution. In some embodiments execution is triggered via a ‘go’ or‘kick’ command in the command sequence. In one embodiment, commandexecution is triggered using a pipeline synchronization command to flushthe command sequence through the graphics pipeline. The 3D pipeline willperform geometry processing for the 3D primitives. Once operations arecomplete, the resulting geometric objects are rasterized and the pixelengine colors the resulting pixels. Additional commands to control pixelshading and pixel back end operations may also be included for thoseoperations.

In some embodiments, the graphics processor command sequence 910 followsthe media pipeline 924 path when performing media operations. Ingeneral, the specific use and manner of programming for the mediapipeline 924 depends on the media or compute operations to be performed.Specific media decode operations may be offloaded to the media pipelineduring media decode. In some embodiments, the media pipeline can also bebypassed and media decode can be performed in whole or in part usingresources provided by one or more general-purpose processing cores. Inone embodiment, the media pipeline also includes elements forgeneral-purpose graphics processor unit (GPGPU) operations, where thegraphics processor is used to perform SIMD vector operations usingcomputational shader programs that are not explicitly related to therendering of graphics primitives.

In some embodiments, media pipeline 924 is configured in a similarmanner as the 3D pipeline 922. A set of commands to configure the mediapipeline state 940 are dispatched or placed into a command queue beforethe media object commands 942. In some embodiments, commands for themedia pipeline state 940 include data to configure the media pipelineelements that will be used to process the media objects. This includesdata to configure the video decode and video encode logic within themedia pipeline, such as encode or decode format. In some embodiments,commands for the media pipeline state 940 also support the use of one ormore pointers to “indirect” state elements that contain a batch of statesettings.

In some embodiments, media object commands 942 supply pointers to mediaobjects for processing by the media pipeline. The media objects includememory buffers containing video data to be processed. In someembodiments, all media pipeline states must be valid before issuing amedia object command 942. Once the pipeline state is configured andmedia obj ect commands 942 are queued, the media pipeline 924 istriggered via an execute command 944 or an equivalent execute event(e.g., register write). Output from media pipeline 924 may then be postprocessed by operations provided by the 3D pipeline 922 or the mediapipeline 924. In some embodiments, GPGPU operations are configured andexecuted in a similar manner as media operations.

Graphics Software Architecture

FIG. 19 illustrates exemplary graphics software architecture for a dataprocessing system 1000 according to some embodiments. In someembodiments, software architecture includes a 3D graphics application1010, an operating system 1020, and at least one processor 1030. In someembodiments, processor 1030 includes a graphics processor 1032 and oneor more general-purpose processor core(s) 1034. The graphics application1010 and operating system 1020 each execute in the system memory 1050 ofthe data processing system.

In some embodiments, 3D graphics application 1010 contains one or moreshader programs including shader instructions 1012. The shader languageinstructions may be in a high-level shader language, such as the HighLevel Shader Language (HLSL) or the OpenGL Shader Language (GLSL). Theapplication also includes executable instructions 1014 in a machinelanguage suitable for execution by the general-purpose processor core1034. The application also includes graphics objects 1016 defined byvertex data.

In some embodiments, operating system 1020 is a Microsoft® Windows®operating system from the Microsoft Corporation, a proprietary UNIX-likeoperating system, or an open source UNIX-like operating system using avariant of the Linux kernel. The operating system 1020 can support agraphics API 1022 such as the Direct3D API, the OpenGL API, or theVulkan API. When the Direct3D API is in use, the operating system 1020uses a front-end shader compiler 1024 to compile any shader instructions1012 in HLSL into a lower-level shader language. The compilation may bea just-in-time (JIT) compilation or the application can perform shaderpre-compilation. In some embodiments, high-level shaders are compiledinto low-level shaders during the compilation of the 3D graphicsapplication 1010. In some embodiments, the shader instructions 1012 areprovided in an intermediate form, such as a version of the StandardPortable Intermediate Representation (SPIR) used by the Vulkan API.

In some embodiments, user mode graphics driver 1026 contains a back-endshader compiler 1027 to convert the shader instructions 1012 into ahardware specific representation. When the OpenGL API is in use, shaderinstructions 1012 in the GLSL high-level language are passed to a usermode graphics driver 1026 for compilation. In some embodiments, usermode graphics driver 1026 uses operating system kernel mode functions1028 to communicate with a kernel mode graphics driver 1029. In someembodiments, kernel mode graphics driver 1029 communicates with graphicsprocessor 1032 to dispatch commands and instructions.

IP Core Implementations

One or more aspects of at least one embodiment may be implemented byrepresentative code stored on a machine-readable medium which representsand/or defines logic within an integrated circuit such as a processor.For example, the machine-readable medium may include instructions whichrepresent various logic within the processor. When read by a machine,the instructions may cause the machine to fabricate the logic to performthe techniques described herein. Such representations, known as “IPcores,” are reusable units of logic for an integrated circuit that maybe stored on a tangible, machine-readable medium as a hardware modelthat describes the structure of the integrated circuit. The hardwaremodel may be supplied to various customers or manufacturing facilities,which load the hardware model on fabrication machines that manufacturethe integrated circuit. The integrated circuit may be fabricated suchthat the circuit performs operations described in association with anyof the embodiments described herein.

FIG. 20A is a block diagram illustrating an IP core development system1100 that may be used to manufacture an integrated circuit to performoperations according to an embodiment. The IP core development system1100 may be used to generate modular, re-usable designs that can beincorporated into a larger design or used to construct an entireintegrated circuit (e.g., an SOC integrated circuit). A design facility1130 can generate a software simulation 1110 of an IP core design in ahigh-level programming language (e.g., C/C++). The software simulation1110 can be used to design, test, and verify the behavior of the IP coreusing a simulation model 1112. The simulation model 1112 may includefunctional, behavioral, and/or timing simulations. A register transferlevel (RTL) design 1115 can then be created or synthesized from thesimulation model 1112. The RTL design 1115 is an abstraction of thebehavior of the integrated circuit that models the flow of digitalsignals between hardware registers, including the associated logicperformed using the modeled digital signals. In addition to an RTLdesign 1115, lower-level designs at the logic level or transistor levelmay also be created, designed, or synthesized. Thus, the particulardetails of the initial design and simulation may vary.

The RTL design 1115 or equivalent may be further synthesized by thedesign facility into a hardware model 1120, which may be in a hardwaredescription language (HDL), or some other representation of physicaldesign data. The HDL may be further simulated or tested to verify the IPcore design. The IP core design can be stored for delivery to a 3rdparty fabrication facility 1165 using non-volatile memory 1140 (e.g.,hard disk, flash memory, or any non-volatile storage medium).Alternatively, the IP core design may be transmitted (e.g., via theInternet) over a wired connection 1150 or wireless connection 1160. Thefabrication facility 1165 may then fabricate an integrated circuit thatis based at least in part on the IP core design. The fabricatedintegrated circuit can be configured to perform operations in accordancewith at least one embodiment described herein.

FIG. 20B illustrates a cross-section side view of an integrated circuitpackage assembly 1170, according to some embodiments described herein.The integrated circuit package assembly 1170 illustrates animplementation of one or more processor or accelerator devices asdescribed herein. The package assembly 1170 includes multiple units ofhardware logic 1172, 1174 connected to a substrate 1180. The logic 1172,1174 may be implemented at least partly in configurable logic orfixed-functionality logic hardware, and can include one or more portionsof any of the processor core(s), graphics processor(s), or otheraccelerator devices described herein. Each unit of logic 1172, 1174 canbe implemented within a semiconductor die and coupled with the substrate1180 via an interconnect structure 1173. The interconnect structure 1173may be configured to route electrical signals between the logic 1172,1174 and the substrate 1180, and can include interconnects such as, butnot limited to bumps or pillars. In some embodiments, the interconnectstructure 1173 may be configured to route electrical signals such as,for example, input/output (I/O) signals and/or power or ground signalsassociated with the operation of the logic 1172, 1174. In someembodiments, the substrate 1180 is an epoxy-based laminate substrate.The package substrate 1180 may include other suitable types ofsubstrates in other embodiments. The package assembly 1170 can beconnected to other electrical devices via a package interconnect 1183.The package interconnect 1183 may be coupled to a surface of thesubstrate 1180 to route electrical signals to other electrical devices,such as a motherboard, other chipset, or multi-chip module.

In some embodiments, the units of logic 1172, 1174 are electricallycoupled with a bridge 1182 that is configured to route electricalsignals between the logic 1172, 1174. The bridge 1182 may be a denseinterconnect structure that provides a route for electrical signals. Thebridge 1182 may include a bridge substrate composed of glass or asuitable semiconductor material. Electrical routing features can beformed on the bridge substrate to provide a chip-to-chip connectionbetween the logic 1172, 1174.

Although two units of logic 1172, 1174 and a bridge 1182 areillustrated, embodiments described herein may include more or fewerlogic units on one or more dies. The one or more dies may be connectedby zero or more bridges, as the bridge 1182 may be excluded when thelogic is included on a single die. Alternatively, multiple dies or unitsof logic can be connected by one or more bridges. Additionally, multiplelogic units, dies, and bridges can be connected together in otherpossible configurations, including three-dimensional configurations.

Exemplary System on a Chip Integrated Circuit

FIGS. 21-23 illustrated exemplary integrated circuits and associatedgraphics processors that may be fabricated using one or more IP cores,according to various embodiments described herein. In addition to whatis illustrated, other logic and circuits may be included, includingadditional graphics processors/cores, peripheral interface controllers,or general-purpose processor cores.

FIG. 21 is a block diagram illustrating an exemplary system on a chipintegrated circuit 1200 that may be fabricated using one or more IPcores, according to an embodiment. Exemplary integrated circuit 1200includes one or more application processor(s) 1205 (e.g., CPUs), atleast one graphics processor 1210, and may additionally include an imageprocessor 1215 and/or a video processor 1220, any of which may be amodular IP core from the same or multiple different design facilities.Integrated circuit 1200 includes peripheral or bus logic including a USBcontroller 1225, UART controller 1230, an SPI/SDIO controller 1235, andan I2S/I2C controller 1240. Additionally, the integrated circuit caninclude a display device 1245 coupled to one or more of ahigh-definition multimedia interface (HDMI) controller 1250 and a mobileindustry processor interface (MIPI) display interface 1255. Storage maybe provided by a flash memory subsystem 1260 including flash memory anda flash memory controller. Memory interface may be provided via a memorycontroller 1265 for access to SDRAM or SRAM memory devices. Someintegrated circuits additionally include an embedded security engine1270.

FIGS. 22A-22B are block diagrams illustrating exemplary graphicsprocessors for use within an SoC, according to embodiments describedherein. FIG. 22A illustrates an exemplary graphics processor 1310 of asystem on a chip integrated circuit that may be fabricated using one ormore IP cores, according to an embodiment. FIG. 22B illustrates anadditional exemplary graphics processor 1340 of a system on a chipintegrated circuit that may be fabricated using one or more IP cores,according to an embodiment. Graphics processor 1310 of FIG. 22A is anexample of a low power graphics processor core. Graphics processor 1340of FIG. 22B is an example of a higher performance graphics processorcore. Each of the graphics processors 1310, 1340 can be variants of thegraphics processor 1210 of FIG. 21.

As shown in FIG. 22A, graphics processor 1310 includes a vertexprocessor 1305 and one or more fragment processor(s) 1315A-1315N (e.g.,1315A, 1315B, 1315C, 1315D, through 1315N-1, and 1315N). Graphicsprocessor 1310 can execute different shader programs via separate logic,such that the vertex processor 1305 is optimized to execute operationsfor vertex shader programs, while the one or more fragment processor(s)1315A-1315N execute fragment (e.g., pixel) shading operations forfragment or pixel shader programs. The vertex processor 1305 performsthe vertex processing stage of the 3D graphics pipeline and generatesprimitives and vertex data. The fragment processor(s) 1315A-1315N usethe primitive and vertex data generated by the vertex processor 1305 toproduce a framebuffer that is displayed on a display device. In oneembodiment, the fragment processor(s) 1315A-1315N are optimized toexecute fragment shader programs as provided for in the OpenGL API,which may be used to perform similar operations as a pixel shaderprogram as provided for in the Direct 3D API.

Graphics processor 1310 additionally includes one or more memorymanagement units (MMUs) 1320A-1320B, cache(s) 1325A-1325B, and circuitinterconnect(s) 1330A-1330B. The one or more MMU(s) 1320A-1320B providefor virtual to physical address mapping for the graphics processor 1310,including for the vertex processor 1305 and/or fragment processor(s)1315A-1315N, which may reference vertex or image/texture data stored inmemory, in addition to vertex or image/texture data stored in the one ormore cache(s) 1325A-1325B. In one embodiment the one or more MMU(s)1320A-1320B may be synchronized with other MMUs within the system,including one or more MMUs associated with the one or more applicationprocessor(s) 1205, image processor 1215, and/or video processor 1220 ofFIG. 21, such that each processor 1205-1220 can participate in a sharedor unified virtual memory system. The one or more circuitinterconnect(s) 1330A-1330B enable graphics processor 1310 to interfacewith other IP cores within the SoC, either via an internal bus of theSoC or via a direct connection, according to embodiments.

As shown FIG. 22B, graphics processor 1340 includes the one or moreMMU(s) 1320A-1320B, caches 1325A-1325B, and circuit interconnects1330A-1330B of the graphics processor 1310 of FIG. 22A. Graphicsprocessor 1340 includes one or more shader core(s) 1355A-1355N (e.g.,1455A, 1355B, 1355C, 1355D, 1355E, 1355F, through 1355N-1, and 1355N),which provides for a unified shader core architecture in which a singlecore or type or core can execute all types of programmable shader code,including shader program code to implement vertex shaders, fragmentshaders, and/or compute shaders. The exact number of shader corespresent can vary among embodiments and implementations. Additionally,graphics processor 1340 includes an inter-core task manager 1345, whichacts as a thread dispatcher to dispatch execution threads to one or moreshader cores 1355A-1355N and a tiling unit 1358 to accelerate tilingoperations for tile-based rendering, in which rendering operations for ascene are subdivided in image space, for example to exploit localspatial coherence within a scene or to optimize use of internal caches.

FIGS. 23A-23B illustrate additional exemplary graphics processor logicaccording to embodiments described herein. FIG. 23A illustrates agraphics core 1400 that may be included within the graphics processor1210 of FIG. 21, and may be a unified shader core 1355A-1355N as in FIG.22B. FIG. 23B illustrates an additional general-purpose graphicsprocessing unit 1430, which is a highly-parallel general-purposegraphics processing unit suitable for deployment on a multi-chip module.

As shown in FIG. 23A, the graphics core 1400 includes a sharedinstruction cache 1402, a texture unit 1418, and a cache/shared memory1420 that are common to the execution resources within the graphics core1400. The graphics core 1400 can include multiple slices 1401A-1401N orpartition for each core, and a graphics processor can include multipleinstances of the graphics core 1400. The slices 1401A-1401N can includesupport logic including a local instruction cache 1404A-1404N, a threadscheduler 1406A-1406N, a thread dispatcher 1408A-1408N, and a set ofregisters 1410A-1440N. To perform logic operations, the slices1401A-1401N can include a set of additional function units (AFUs1412A-1412N), floating-point units (FPU 1414A-1414N), integer arithmeticlogic units (ALUs 1416-1416N), address computational units (ACU1413A-1413N), double-precision floating-point units (DPFPU 1415A-1415N),and matrix processing units (MPU 1417A-1417N).

Some of the computational units operate at a specific precision. Forexample, the FPUs 1414A-1414N can perform single-precision (32-bit) andhalf-precision (16-bit) floating point operations, while the DPFPUs1415A-1415N perform double precision (64-bit) floating point operations.The ALUs 1416A-1416N can perform variable precision integer operationsat 8-bit, 16-bit, and 32-bit precision, and can be configured for mixedprecision operations. The MPUs 1417A-1417N can also be configured formixed precision matrix operations, including half-precision floatingpoint and 8-bit integer operations. The MPUs 1417-1417N can perform avariety of matrix operations to accelerate machine learning applicationframeworks, including enabling support for accelerated general matrix tomatrix multiplication (GEMM). The AFUs 1412A-1412N can performadditional logic operations not supported by the floating-point orinteger units, including trigonometric operations (e.g., Sine, Cosine,etc.).

As shown in FIG. 23B, a general-purpose processing unit (GPGPU) 1430 canbe configured to enable highly-parallel compute operations to beperformed by an array of graphics processing units. Additionally, theGPGPU 1430 can be linked directly to other instances of the GPGPU tocreate a multi-GPU cluster to improve training speed for particularlydeep neural networks. The GPGPU 1430 includes a host interface 1432 toenable a connection with a host processor. In one embodiment the hostinterface 1432 is a PCI Express interface. However, the host interfacecan also be a vendor specific communications interface or communicationsfabric. The GPGPU 1430 receives commands from the host processor anduses a global scheduler 1434 to distribute execution threads associatedwith those commands to a set of compute clusters 1436A-1436H. Thecompute clusters 1436A-1436H share a cache memory 1438. The cache memory1438 can serve as a higher-level cache for cache memories within thecompute clusters 1436A-1436H.

The GPGPU 1430 includes memory 1444A-1444B coupled with the computeclusters 1436A-1436H via a set of memory controllers 1442A-1442B. Invarious embodiments, the memory 1434A-1434B can include various types ofmemory devices including dynamic random access memory (DRAM) or graphicsrandom access memory, such as synchronous graphics random access memory(SGRAM), including graphics double data rate (GDDR) memory.

In one embodiment the compute clusters 1436A-1436H each include a set ofgraphics cores, such as the graphics core 1400 of FIG. 23A, which caninclude multiple types of integer and floating point logic units thatcan perform computational operations at a range of precisions includingsuited for machine learning computations. For example and in oneembodiment at least a subset of the floating point units in each of thecompute clusters 1436A-1436H can be configured to perform 16-bit or32-bit floating point operations, while a different subset of thefloating point units can be configured to perform 64-bit floating pointoperations.

Multiple instances of the GPGPU 1430 can be configured to operate as acompute cluster. The communication mechanism used by the compute clusterfor synchronization and data exchange varies across embodiments. In oneembodiment the multiple instances of the GPGPU 1430 communicate over thehost interface 1432. In one embodiment the GPGPU 1430 includes an I/Ohub 1439 that couples the GPGPU 1430 with a GPU link 1440 that enables adirect connection to other instances of the GPGPU. In one embodiment theGPU link 1440 is coupled to a dedicated GPU-to-GPU bridge that enablescommunication and synchronization between multiple instances of theGPGPU 1430. In one embodiment the GPU link 1440 couples with a highspeed interconnect to transmit and receive data to other GPGPUs orparallel processors. In one embodiment the multiple instances of theGPGPU 1430 are located in separate data processing systems andcommunicate via a network device that is accessible via the hostinterface 1432. In one embodiment the GPU link 1440 can be configured toenable a connection to a host processor in addition to or as analternative to the host interface 1432.

While the illustrated configuration of the GPGPU 1430 can be configuredto train neural networks, one embodiment provides alternateconfiguration of the GPGPU 1430 that can be configured for deploymentwithin a high performance or low power inferencing platform. In aninferencing configuration the GPGPU 1430 includes fewer of the computeclusters 1436A-1436H relative to the training configuration.Additionally, the memory technology associated with the memory1434A-1434B may differ between inferencing and training configurations,with higher bandwidth memory technologies devoted to trainingconfigurations. In one embodiment the inferencing configuration of theGPGPU 1430 can support inferencing specific instructions. For example,an inferencing configuration can provide support for one or more 8-bitinteger dot product instructions, which are commonly used duringinferencing operations for deployed neural networks.

Advantageously, any of the above systems, processors, graphicsprocessors, apparatuses, and/or methods may be integrated or configuredwith any of the various embodiments described herein (e.g., or portionsthereof), including, for example, those described in the belowAdditional Notes and Examples.

In one example, the processor(s) 102 (FIG. 10) and/or the graphicsprocessors 108 (FIG. 10) receive image data from multiple cameras 144(FIG. 10), and implement one or more aspects of the method 50 (FIG. 4),the method 62 (FIG. 5) and/or the method 92 (FIG. 8). Additionally, thelogic 1172 (FIG. 20B) and/or the logic 1174 (FIG. 20B) may implement oneor more aspects of the method 50 (FIG. 4), the method 62 (FIG. 5) and/orthe method 92 (FIG. 8). Moreover, in some embodiments, the graphicsprocessor instruction formats 700 may be adapted for use in the system150 (FIG. 9), with suitable instructions to implement one or moreaspects of those embodiments. The technology described herein thereforeenables the automated adjustment of pre-stitch parameters.

Additional Notes and Examples:

Example 1 includes a performance-enhanced computing system comprisingone or more camera sensors to generate a pair of images corresponding toa first eye and a reference image corresponding to a second eye, agraphics processor including one or more substrates and logic coupled tothe one or more substrates, wherein the logic is implemented at leastpartly in one or more of configurable logic or fixed-functionalityhardware logic, the logic coupled to the one or more substrates toidentify a seam area between the pair of images, determine a disparitybetween the seam area and a reference area at a center line of thereference image, and adjust one or more pre-stitch parameters of the oneor more camera sensors based on the disparity.

Example 2 includes the computing system of Example 1, wherein the logiccoupled to the one or more substrates is to compensate the disparity forone or more of lens distortion or geometric distortion.

Example 3 includes the computing system of Example 1, wherein the logiccoupled to the one or more substrates is to identify a first set ofnodal positions in the seam area based on a feature map, and identify asecond set of nodal positions in the reference area based on the firstset of nodal positions, wherein the disparity is determined between thefirst set of nodal positions and the second set of nodal positions.

Example 4 includes the computing system of Example 1, wherein the logiccoupled to the one or more substrates is to trigger a readjustment ofthe one or more pre-stitch parameters in response to one or more of adetected motion at the one or more camera sensors or a detected ambientlight change at the one or more camera sensors.

Example 5 includes the computing system of Example 1, wherein the one ormore camera sensors includes a pair of first eye camera sensors togenerate the pair of images and a second eye camera to generate thereference image, and wherein the second eye camera sensor is positionedbetween the pair of first eye camera sensors.

Example 6 includes the computing system of Example 1, wherein the one ormore camera sensors includes a first camera sensor to generate a firstimage of the pair of images and the reference image and a second camerasensor to generate a second image of the pair of images, and wherein thereference image corresponds to the first camera sensor in a rotatedstate.

Example 7 includes the computing system of any one of Examples 1 to 6,wherein the one or more pre-stitch parameters include one or more of acolor parameter, a reference area width, an alignment or an orientation.

Example 8 includes a semiconductor apparatus comprising one or moresubstrates, and logic coupled to the one or more substrates, wherein thelogic is implemented at least partly in one or more of configurablelogic or fixed-functionality hardware logic, the logic coupled to theone or more substrates to identify a seam area between a pair of imagescorresponding to a first eye, determine a disparity between the seamarea and a reference area at a center line of a reference imagecorresponding to a second eye, and adjust one or more pre-stitchparameters of camera sensors associated with the pair of images and thereference image based on the disparity.

Example 9 includes the semiconductor apparatus of Example 8, wherein thelogic coupled to the one or more substrates is to compensate thedisparity for one or more of lens distortion or geometric distortion.

Example 10 includes the semiconductor apparatus of Example 8, whereinthe logic coupled to the one or more substrates is to identify a firstset of nodal positions in the seam area based on a feature map, andidentify a second set of nodal positions in the reference area based onthe first set of nodal positions, wherein the disparity is determinedbetween the first set of nodal positions and the second set of nodalpositions.

Example 11 includes the semiconductor apparatus of Example 8, whereinthe logic coupled to the one or more substrates is to trigger areadjustment of the one or more pre-stitch parameters in response to oneor more of a detected motion at the camera sensors or a detected ambientlight change at the camera sensors.

Example 12 includes the semiconductor apparatus of Example 8, whereinthe reference image is to be associated with a second eye camera sensorpositioned between a pair of first eye camera sensors associated withthe pair of images.

Example 13 includes the semiconductor apparatus of any one of Examples 8to 12, wherein the one or more pre-stitch parameters include one or moreof a color parameter, a reference area width, an alignment or anorientation.

Example 14 includes at least one computer readable storage mediumcomprising a set of instructions, which when executed by a computingsystem, cause the computing system to identify a seam area between apair of images corresponding to a first eye, determine a disparitybetween the seam area and a reference area at a center line of areference image corresponding to a second eye, and adjust one or morepre-stitch parameters of camera sensors associated with the pair ofimages and the reference image based on the disparity.

Example 15 includes the at least one computer readable storage medium ofExample 14, wherein the instructions, when executed, cause the computingsystem to compensate the disparity for one or more of lens distortion orgeometric distortion.

Example 16 includes the at least one computer readable storage medium ofExample 14, wherein the instructions, when executed, cause the computingsystem to identify a first set of nodal positions in the seam area basedon a feature map, and identify a second set of nodal positions in thereference area based on the first set of nodal positions, wherein thedisparity is determined between the first set of nodal positions and thesecond set of nodal positions.

Example 17 includes the at least one computer readable storage medium ofExample 14, wherein the instructions, when executed, cause the computingsystem to trigger a readjustment of the one or more pre-stitchparameters in response to one or more of a detected motion at the camerasensors or a detected ambient light change at the camera sensors.

Example 18 includes the at least one computer readable storage medium ofExample 14, wherein the reference image is to be associated with asecond eye camera sensor positioned between a pair of first eye camerasensors associated with the pair of images.

Example 19 includes the at least one computer readable storage medium ofany one of Examples 14 to 18, wherein the one or more pre-stitchparameters include one or more of a color parameter, a reference areawidth, an alignment or an orientation.

Example 20 includes a method comprising identifying a seam area betweena pair of images corresponding to a first eye, determining a disparitybetween the seam area and a reference area at a center line of areference image corresponding to a second eye, and adjusting one or morepre-stitch parameters of camera sensors associated with the pair ofimages and the reference image based on the disparity.

Example 21 includes the method of Example 20, further includingcompensating the disparity for one or more of lens distortion orgeometric distortion.

Example 22 includes the method of Example 20, further includingidentifying a first set of nodal positions in the seam area based on afeature map, and identifying a second set of nodal positions in thereference area based on the first set of nodal positions, wherein thedisparity is determined between the first set of nodal positions and thesecond set of nodal positions.

Example 23 includes the method of Example 20, further includingtriggering a readjustment of the one or more pre-stitch parameters inresponse to one or more of a detected motion at the camera sensors or adetected ambient light change at the camera sensors.

Example 24 includes the method of Example 20, wherein the referenceimage is associated with a second eye camera sensor positioned between apair of first eye camera sensors associated with the pair of images.

Example 25 includes the method of any one of Examples 20 to 24, whereinthe one or more pre-stitch parameters include one or more of a colorparameter, a reference area width, an alignment or an orientation.

Example 26 includes means for performing the method of any of Examples20 to 25.

Embodiments are applicable for use with all types of semiconductorintegrated circuit (“IC”) chips. Examples of these IC chips include butare not limited to processors, controllers, chipset components,programmable logic arrays (PLAs), memory chips, network chips, systemson chip (SoCs), SSD/NAND controller ASICs, and the like. In addition, insome of the drawings, signal conductor lines are represented with lines.Some may be different, to indicate more constituent signal paths, have anumber label, to indicate a number of constituent signal paths, and/orhave arrows at one or more ends, to indicate primary information flowdirection. This, however, should not be construed in a limiting manner.Rather, such added detail may be used in connection with one or moreexemplary embodiments to facilitate easier understanding of a circuit.Any represented signal lines, whether or not having additionalinformation, may actually comprise one or more signals that may travelin multiple directions and may be implemented with any suitable type ofsignal scheme, e.g., digital or analog lines implemented withdifferential pairs, optical fiber lines, and/or single-ended lines.

Example sizes/models/values/ranges may have been given, althoughembodiments are not limited to the same. As manufacturing techniques(e.g., photolithography) mature over time, it is expected that devicesof smaller size could be manufactured. In addition, well knownpower/ground connections to IC chips and other components may or may notbe shown within the figures, for simplicity of illustration anddiscussion, and so as not to obscure certain aspects of the embodiments.Further, arrangements may be shown in block diagram form in order toavoid obscuring embodiments, and also in view of the fact that specificswith respect to implementation of such block diagram arrangements arehighly dependent upon the platform within which the embodiment is to beimplemented, i.e., such specifics should be well within purview of oneskilled in the art. Where specific details (e.g., circuits) are setforth in order to describe example embodiments, it should be apparent toone skilled in the art that embodiments can be practiced without, orwith variation of, these specific details. The description is thus to beregarded as illustrative instead of limiting.

The term “coupled” may be used herein to refer to any type ofrelationship, direct or indirect, between the components in question,and may apply to electrical, mechanical, fluid, optical,electromagnetic, electromechanical or other connections. In addition,the terms “first”, “second”, etc. may be used herein only to facilitatediscussion, and carry no particular temporal or chronologicalsignificance unless otherwise indicated.

As used in this application and in the claims, a list of items joined bythe term “one or more of” may mean any combination of the listed terms.For example, the phrase “one or more of A, B, and C” and the phrase “oneor more of A, B, or C” both may mean A; B; C; A and B; A and C; B and C;or A, B and C.

Those skilled in the art will appreciate from the foregoing descriptionthat the broad techniques of the embodiments can be implemented in avariety of forms. Therefore, while the embodiments have been describedin connection with particular examples thereof, the true scope of theembodiments should not be so limited since other modifications willbecome apparent to the skilled practitioner upon a study of thedrawings, specification, and following claims.

We claim:
 1. A computing system comprising: one or more camera sensorsto generate a pair of images corresponding to a first eye and areference image corresponding to a second eye; a graphics processorincluding one or more substrates and logic coupled to the one or moresubstrates, wherein the logic is implemented at least partly in one ormore of configurable logic or fixed-functionality hardware logic, thelogic coupled to the one or more substrates to: identify a seam areabetween the pair of images, determine a disparity between the seam areaand a reference area at a center line of the reference image, and adjustone or more pre-stitch parameters of the one or more camera sensorsbased on the disparity.
 2. The computing system of claim 1, wherein thelogic coupled to the one or more substrates is to compensate thedisparity for one or more of lens distortion or geometric distortion. 3.The computing system of claim 1, wherein the logic coupled to the one ormore substrates is to: identify a first set of nodal positions in theseam area based on a feature map, and identify a second set of nodalpositions in the reference area based on the first set of nodalpositions, wherein the disparity is determined between the first set ofnodal positions and the second set of nodal positions.
 4. The computingsystem of claim 1, wherein the logic coupled to the one or moresubstrates is to trigger a readjustment of the one or more pre-stitchparameters in response to one or more of a detected motion at the one ormore camera sensors or a detected ambient light change at the one ormore camera sensors.
 5. The computing system of claim 1, wherein the oneor more camera sensors includes a pair of first eye camera sensors togenerate the pair of images and a second eye camera to generate thereference image, and wherein the second eye camera sensor is positionedbetween the pair of first eye camera sensors.
 6. The computing system ofclaim 1, wherein the one or more camera sensors includes a first camerasensor to generate a first image of the pair of images and the referenceimage and a second camera sensor to generate a second image of the pairof images, and wherein the reference image corresponds to the firstcamera sensor in a rotated state.
 7. The computing system of claim 1,wherein the one or more pre-stitch parameters include one or more of acolor parameter, a reference area width, an alignment or an orientation.8. A semiconductor apparatus comprising: one or more substrates; andlogic coupled to the one or more substrates, wherein the logic isimplemented at least partly in one or more of configurable logic orfixed-functionality hardware logic, the logic coupled to the one or moresubstrates to: identify a seam area between a pair of imagescorresponding to a first eye; determine a disparity between the seamarea and a reference area at a center line of a reference imagecorresponding to a second eye; and adjust one or more pre-stitchparameters of camera sensors associated with the pair of images and thereference image based on the disparity.
 9. The semiconductor apparatusof claim 8, wherein the logic coupled to the one or more substrates isto compensate the disparity for one or more of lens distortion orgeometric distortion.
 10. The semiconductor apparatus of claim 8,wherein the logic coupled to the one or more substrates is to: identifya first set of nodal positions in the seam area based on a feature map;and identify a second set of nodal positions in the reference area basedon the first set of nodal positions, wherein the disparity is determinedbetween the first set of nodal positions and the second set of nodalpositions.
 11. The semiconductor apparatus of claim 8, wherein the logiccoupled to the one or more substrates is to trigger a readjustment ofthe one or more pre-stitch parameters in response to one or more of adetected motion at the camera sensors or a detected ambient light changeat the camera sensors.
 12. The semiconductor apparatus of claim 8,wherein the reference image is to be associated with a second eye camerasensor positioned between a pair of first eye camera sensors associatedwith the pair of images.
 13. The semiconductor apparatus of claim 8,wherein the one or more pre-stitch parameters include one or more of acolor parameter, a reference area width, an alignment or an orientation.14. At least one computer readable storage medium comprising a set ofinstructions, which when executed by a computing system, cause thecomputing system to: identify a seam area between a pair of imagescorresponding to a first eye; determine a disparity between the seamarea and a reference area at a center line of a reference imagecorresponding to a second eye; and adjust one or more pre-stitchparameters of camera sensors associated with the pair of images and thereference image based on the disparity.
 15. The at least one computerreadable storage medium of claim 14, wherein the instructions, whenexecuted, cause the computing system to compensate the disparity for oneor more of lens distortion or geometric distortion.
 16. The at least onecomputer readable storage medium of claim 14, wherein the instructions,when executed, cause the computing system to: identify a first set ofnodal positions in the seam area based on a feature map; and identify asecond set of nodal positions in the reference area based on the firstset of nodal positions, wherein the disparity is determined between thefirst set of nodal positions and the second set of nodal positions. 17.The at least one computer readable storage medium of claim 14, whereinthe instructions, when executed, cause the computing system to trigger areadjustment of the one or more pre-stitch parameters in response to oneor more of a detected motion at the camera sensors or a detected ambientlight change at the camera sensors.
 18. The at least one computerreadable storage medium of claim 14, wherein the reference image is tobe associated with a second eye camera sensor positioned between a pairof first eye camera sensors associated with the pair of images.
 19. Theat least one computer readable storage medium of claim 14, wherein theone or more pre-stitch parameters include one or more of a colorparameter, a reference area width, an alignment or an orientation.
 20. Amethod comprising: identifying a seam area between a pair of imagescorresponding to a first eye; determining a disparity between the seamarea and a reference area at a center line of a reference imagecorresponding to a second eye; and adjusting one or more pre-stitchparameters of camera sensors associated with the pair of images and thereference image based on the disparity.
 21. The method of claim 20,further including compensating the disparity for one or more of lensdistortion or geometric distortion.
 22. The method of claim 20, furtherincluding: identifying a first set of nodal positions in the seam areabased on a feature map; and identifying a second set of nodal positionsin the reference area based on the first set of nodal positions, whereinthe disparity is determined between the first set of nodal positions andthe second set of nodal positions.
 23. The method of claim 20, furtherincluding triggering a readjustment of the one or more pre-stitchparameters in response to one or more of a detected motion at the camerasensors or a detected ambient light change at the camera sensors. 24.The method of claim 20, wherein the reference image is associated with asecond eye camera sensor positioned between a pair of first eye camerasensors associated with the pair of images.
 25. The method of claim 20,wherein the one or more pre-stitch parameters include one or more of acolor parameter, a reference area width, an alignment or an orientation.